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    Uniprocessor Virtual Memory Without TLBs

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    Uniprocessor_rights.pdf (849.7Kb)
    No. of downloads: 750

    Date
    2001-05
    Author
    Jacob, Bruce
    Mudge, Trevor
    Citation
    "Uniprocessor virtual memory without TLBs." Bruce Jacob and Trevor Mudge. IEEE Transactions on Computers, vol. 50, no. 5, pp. 482-499. May 2001.001
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    Abstract
    We present a feasibility study for performing virtual address translation without specialized translation hardware. Removing address translation hardware and instead managing address translation in software has the potential to make the processor design simpler, smaller, and more energy-efficient at little or no cost in performance. The purpose of this study is to describe the design and quantify its performance impact. Trace-driven simulations show that software-managed address translation is just as efficient as hardware-managed address translation. Moreover, mechanisms to support such features such as shared memory, superpages, fine-grained protection, and sparse address spaces can be defined completely in software, allowing for more flexibility than in hardware-defined mechanisms.
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    http://hdl.handle.net/1903/7461
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    • Electrical & Computer Engineering Research Works

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