Uniprocessor Virtual Memory Without TLBs

dc.contributor.authorJacob, Bruce
dc.contributor.authorMudge, Trevor
dc.date.accessioned2007-11-08T18:48:31Z
dc.date.available2007-11-08T18:48:31Z
dc.date.issued2001-05
dc.description.abstractWe present a feasibility study for performing virtual address translation without specialized translation hardware. Removing address translation hardware and instead managing address translation in software has the potential to make the processor design simpler, smaller, and more energy-efficient at little or no cost in performance. The purpose of this study is to describe the design and quantify its performance impact. Trace-driven simulations show that software-managed address translation is just as efficient as hardware-managed address translation. Moreover, mechanisms to support such features such as shared memory, superpages, fine-grained protection, and sparse address spaces can be defined completely in software, allowing for more flexibility than in hardware-defined mechanisms.en
dc.format.extent870180 bytes
dc.format.mimetypeapplication/pdf
dc.identifier.citation"Uniprocessor virtual memory without TLBs." Bruce Jacob and Trevor Mudge. IEEE Transactions on Computers, vol. 50, no. 5, pp. 482-499. May 2001.001en
dc.identifier.urihttp://hdl.handle.net/1903/7461
dc.language.isoen_USen
dc.publisherIEEEen
dc.relation.isAvailableAtA. James Clark School of Engineeringen_us
dc.relation.isAvailableAtElectrical & Computer Engineeringen_us
dc.relation.isAvailableAtDigital Repository at the University of Marylanden_us
dc.relation.isAvailableAtUniversity of Maryland (College Park, MD)en_us
dc.subjectvirtual memoryen
dc.subjectvirtual address translationen
dc.subjectvirtual cachesen
dc.subjectmemory managementen
dc.subjectsoftware-managed address translationen
dc.subjecttranslation lookaside buffers (TLBs)en
dc.titleUniprocessor Virtual Memory Without TLBsen
dc.typeArticleen

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