Dual-Processor Design of Energy Efficient Fault-Tolerant System
| dc.contributor.author | Hua, Shaoxiong | |
| dc.contributor.author | Pari, Pushkin R. | |
| dc.contributor.author | Qu, Gang | |
| dc.date.accessioned | 2009-05-11T16:09:41Z | |
| dc.date.available | 2009-05-11T16:09:41Z | |
| dc.date.issued | 2006-09 | |
| dc.description.abstract | A popular approach to guarantee fault tolerance in safety-critical applications is to run the application on two processors. A checkpoint is inserted at the comple- tion of the primary copy. If there is no fault, the sec- ondary processor terminates its execution. Otherwise, should the fault occur, the second processor continues and completes the application before its deadline. In this paper, we study the energy efficiency of such dual- processor system. Specifically, we first derive an opti- mal static voltage scaling policy for single periodic task. We then extend it to multiple periodic tasks based on worst case execution time (WCET) analysis. Finally, we discuss how to further reduce system’s energy con- sumption at run time by taking advantage of the actual execution time which is less than the WCET. Simula- tion on real-life benchmark applications shows that our technique can save up to 80% energy while still provid- ing fault tolerance. | en |
| dc.format.extent | 343148 bytes | |
| dc.format.mimetype | application/pdf | |
| dc.identifier.citation | S. Hua, P.R. Pari, and G. Qu. "Dual-Processor Design of Energy Efficient Fault-Tolerant System," 17th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP'06), pp. 239-244, September 2006. | en |
| dc.identifier.uri | http://hdl.handle.net/1903/9071 | |
| dc.language.iso | en_US | en |
| dc.publisher | IEEE | en |
| dc.relation.isAvailableAt | A. James Clark School of Engineering | en_us |
| dc.relation.isAvailableAt | Electrical & Computer Engineering | en_us |
| dc.relation.isAvailableAt | Digital Repository at the University of Maryland | en_us |
| dc.relation.isAvailableAt | University of Maryland (College Park, MD) | en_us |
| dc.rights.license | Copyright © 2006 IEEE. Reprinted from 17th IEEE International Conference on Application-specific Systems, Architectures and Processors. This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of the University of Maryland's products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to pubs-permissions@ieee.org. By choosing to view this document, you agree to all provisions of the copyright laws protecting it. | |
| dc.subject | fault tolerance | en |
| dc.subject | processors | en |
| dc.subject | energy consumption | en |
| dc.title | Dual-Processor Design of Energy Efficient Fault-Tolerant System | en |
| dc.type | Article | en |