Dual-Processor Design of Energy Efficient Fault-Tolerant System

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2006-09

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S. Hua, P.R. Pari, and G. Qu. "Dual-Processor Design of Energy Efficient Fault-Tolerant System," 17th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP'06), pp. 239-244, September 2006.

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Abstract

A popular approach to guarantee fault tolerance in safety-critical applications is to run the application on two processors. A checkpoint is inserted at the comple- tion of the primary copy. If there is no fault, the sec- ondary processor terminates its execution. Otherwise, should the fault occur, the second processor continues and completes the application before its deadline. In this paper, we study the energy efficiency of such dual- processor system. Specifically, we first derive an opti- mal static voltage scaling policy for single periodic task. We then extend it to multiple periodic tasks based on worst case execution time (WCET) analysis. Finally, we discuss how to further reduce system’s energy con- sumption at run time by taking advantage of the actual execution time which is less than the WCET. Simula- tion on real-life benchmark applications shows that our technique can save up to 80% energy while still provid- ing fault tolerance.

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