Fully-Buffered DIMM Memory Architectures: Understanding Mechanisms, Overheads and Scaling
| dc.contributor.author | Ganesh, Brinda | |
| dc.contributor.author | Jaleel, Aamer | |
| dc.contributor.author | Wang, David | |
| dc.contributor.author | Jacob, Bruce | |
| dc.date.accessioned | 2007-11-08T18:39:54Z | |
| dc.date.available | 2007-11-08T18:39:54Z | |
| dc.date.issued | 2007-02 | |
| dc.description.abstract | Performance gains in memory have traditionally been obtained by increasing memory bus widths and speeds. The diminishing returns of such techniques have led to the proposal of an alternate architecture, the Fully-Buffered DIMM. This new standard replaces the conventional memory bus with a narrow, high-speed interface between the memory controller and the DIMMs. This paper examines how traditional DDRx based memory controller policies for scheduling and row buffer management perform on a Fully- Buffered DIMM memory architecture. The split-bus architecture used by FBDIMM systems results in an average improvement of 7% in latency and 10% in bandwidth at higher utilizations. On the other hand, at lower utilizations, the increased cost of serialization resulted in a degradation in latency and bandwidth of 25% and 10% respectively. The split-bus architecture also makes the system performance sensitive to the ratio of read and write traffic in the workload. In larger configurations, we found that the FBDIMM system performance was more sensitive to usage of the FBDIMM links than to DRAM bank availability. In general, FBDIMM performance is similar to that of DDRx systems, and provides better performance characteristics at higher utilization, making it a relatively inexpensive mechanism for scaling capacity at higher bandwidth requirements. The mechanism is also largely insensitive to scheduling policies, provided certain ground rules are obeyed. | en |
| dc.format.extent | 512384 bytes | |
| dc.format.mimetype | application/pdf | |
| dc.identifier.citation | "Fully-Buffered DIMM memory architectures: Understanding mechanisms, overheads and scaling." Brinda Ganesh, Aamer Jaleel, David Wang, and Bruce Jacob. Proc. 13th International Symposium on High Performance Computer Architecture (HPCA 2007). Phoenix AZ, February 2007. | en |
| dc.identifier.uri | http://hdl.handle.net/1903/7448 | |
| dc.language.iso | en_US | en |
| dc.relation.isAvailableAt | A. James Clark School of Engineering | en_us |
| dc.relation.isAvailableAt | Electrical & Computer Engineering | en_us |
| dc.relation.isAvailableAt | Digital Repository at the University of Maryland | en_us |
| dc.relation.isAvailableAt | University of Maryland (College Park, MD) | en_us |
| dc.subject | fully-buffered DIMM | en |
| dc.subject | memory bus | en |
| dc.subject | bandwidth | en |
| dc.title | Fully-Buffered DIMM Memory Architectures: Understanding Mechanisms, Overheads and Scaling | en |
| dc.type | Presentation | en |