ARBITRATE-AND-MOVE PRIMITIVES FOR HIGH THROUGHPUT ON-CHIP INTERCONNECTION NETWORKS
| dc.contributor.author | Balkan, Aydin O. | |
| dc.contributor.author | Vishkin, U. | |
| dc.contributor.author | Qu, Gang | |
| dc.date.accessioned | 2009-05-11T13:53:25Z | |
| dc.date.available | 2009-05-11T13:53:25Z | |
| dc.date.issued | 2004-05 | |
| dc.description.abstract | An n-leaf pipelined balanced binary tree is used for arbitration of order and movement of data from n input ports to one output port. A novel arbitrate-and-move primitive circuit for every node of the tree, which is based on a concept of reduced synchrony that benefits from attractive features of both asynchronous and synchronous designs, is presented. The design objective of the pipelined binary tree is to provide a key building block in a high-throughput mesh-of-trees interconnection network for Explicit Multi Threading (XMT) architecture, a recently introduced parallel computation framework. The proposed reduced synchrony circuit was compared with asynchronous and synchronous designs of arbitrate-and-move primitives. Simulations with 0.18m technology show that compared to an asynchronous design, the proposed reduced synchrony implementation achieves a higher throughput, up to 2 Giga- Requests per second on an 8-leaf binary tree. Our circuit also consumes less power than the synchronous design, and requires less silicon area than both the synchronous and asynchronous designs. | en |
| dc.format.extent | 279647 bytes | |
| dc.format.mimetype | application/pdf | |
| dc.identifier.citation | A. Balkan, G. Qu, and U. Vishkin. "Arbitrate-and-Move Primitives for High Throughput On-Chip Interconnection Networks," IEEE International Symposium on Circuits and Systems, Vol. 2, pp. 441-444, May 2004. | en |
| dc.identifier.uri | http://hdl.handle.net/1903/9064 | |
| dc.language.iso | en_US | en |
| dc.publisher | IEEE | en |
| dc.relation.isAvailableAt | A. James Clark School of Engineering | en_us |
| dc.relation.isAvailableAt | Electrical & Computer Engineering | en_us |
| dc.relation.isAvailableAt | Digital Repository at the University of Maryland | en_us |
| dc.relation.isAvailableAt | University of Maryland (College Park, MD) | en_us |
| dc.rights.license | Copyright © 2004 IEEE. Reprinted from IEEE International Symposium on Circuits and Systems. This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of the University of Maryland's products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to pubs-permissions@ieee.org. By choosing to view this document, you agree to all provisions of the copyright laws protecting it. | |
| dc.subject | n-leaf | en |
| dc.subject | power consumption | en |
| dc.title | ARBITRATE-AND-MOVE PRIMITIVES FOR HIGH THROUGHPUT ON-CHIP INTERCONNECTION NETWORKS | en |
| dc.type | Article | en |
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