Power Optimization of Variable Voltage Core-Based Systems

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dc.contributor.authorHong, Inki
dc.contributor.authorKirovski, Darko
dc.contributor.authorQu, Gang
dc.contributor.authorPotkonjak, Miodrag
dc.contributor.authorSrivastava, Mani B.
dc.date.accessioned2009-03-12T12:42:30Z
dc.date.available2009-03-12T12:42:30Z
dc.date.issued1999-12
dc.description.abstractThe growing class of portable systems, such as personal computing and communication devices, has resulted in a new set of system design requirements, mainly characterized by dominant importance of power minimization and design reuse. The energy efficiency of systems-on-a-chip (SOC) could be much improved if one were to vary the supply voltage dynamically at run time. We develop the design methodology for the lowpower core-based real-time SOC based on dynamically variable voltage hardware. The key challenge is to develop effective scheduling techniques that treat voltage as a variable to be determined, in addition to the conventional task scheduling and allocation. Our synthesis technique also addresses the selection of the processor core and the determination of the instruction and data cache size and configuration so as to fully exploit dynamically variable voltage hardware, which results in significantly lower power consumption for a set of target applications than existing techniques. The highlight of the proposed approach is the nonpreemptive scheduling heuristic, which results in solutions very close to optimal ones for many test cases. The effectiveness of the approach is demonstrated on a variety of modern industrial strength multimedia and communication applications.en
dc.format.extent289792 bytes
dc.format.mimetypeapplication/pdf
dc.identifier.citationI. Hong, D. Kirovski, G. Qu, M. Potkonjak, and M. Srivastava, "Power Optimization of Variable Voltage Core-Based Systems," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 18, No. 12, pp. 1702-1714, December 1999.en
dc.identifier.urihttp://hdl.handle.net/1903/8951
dc.language.isoen_USen
dc.publisherIEEEen
dc.relation.isAvailableAtA. James Clark School of Engineeringen_us
dc.relation.isAvailableAtElectrical & Computer Engineeringen_us
dc.relation.isAvailableAtDigital Repository at the University of Marylanden_us
dc.relation.isAvailableAtUniversity of Maryland (College Park, MD)en_us
dc.rights.licenseCopyright © 1999 IEEE. Reprinted from IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of the University of Maryland's products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to pubs-permissions@ieee.org. By choosing to view this document, you agree to all provisions of the copyright laws protecting it.
dc.subjecthigh-level synthesisen
dc.subjectschedulingen
dc.subjectsynthesis for low poweren
dc.subjectsystem-on-a-chip (SOC)en
dc.titlePower Optimization of Variable Voltage Core-Based Systemsen
dc.typeArticleen

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