Power Optimization of Variable Voltage Core-Based Systems
Power Optimization of Variable Voltage Core-Based Systems
Loading...
Files
Publication or External Link
Date
1999-12
Authors
Hong, Inki
Kirovski, Darko
Qu, Gang
Potkonjak, Miodrag
Srivastava, Mani B.
Advisor
Citation
I. Hong, D. Kirovski, G. Qu, M. Potkonjak, and M. Srivastava, "Power Optimization of Variable Voltage Core-Based Systems," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 18, No. 12, pp. 1702-1714, December 1999.
DRUM DOI
Abstract
The growing class of portable systems, such as
personal computing and communication devices, has resulted in a
new set of system design requirements, mainly characterized by
dominant importance of power minimization and design reuse.
The energy efficiency of systems-on-a-chip (SOC) could be much
improved if one were to vary the supply voltage dynamically
at run time. We develop the design methodology for the lowpower
core-based real-time SOC based on dynamically variable
voltage hardware. The key challenge is to develop effective
scheduling techniques that treat voltage as a variable to be
determined, in addition to the conventional task scheduling and
allocation. Our synthesis technique also addresses the selection of
the processor core and the determination of the instruction and
data cache size and configuration so as to fully exploit dynamically
variable voltage hardware, which results in significantly
lower power consumption for a set of target applications than
existing techniques. The highlight of the proposed approach is
the nonpreemptive scheduling heuristic, which results in solutions
very close to optimal ones for many test cases. The effectiveness of
the approach is demonstrated on a variety of modern industrial strength
multimedia and communication applications.