A Combined Gate Replacement and Input Vector Control Approach for Leakage Current Reduction

dc.contributor.authorYuan, Lin
dc.contributor.authorQu, Gang
dc.date.accessioned2009-03-12T12:44:19Z
dc.date.available2009-03-12T12:44:19Z
dc.date.issued2006-02
dc.description.abstractInput vector control (IVC) is a popular technique for leakage power reduction. It utilizes the transistor stack effect in CMOS gates by applying a minimum leakage vector (MLV) to the primary inputs of combinational circuits during the standby mode. However, the IVC technique becomes less effective for circuits of large logic depth because the input vector at primary inputs has little impact on leakage of internal gates at high logic levels. In this paper, we propose a technique to overcome this limitation by replacing those internal gates in their worst leakage states by other library gates while maintaining the circuit’s correct functionality during the active mode. This modification of the circuit does not require changes of the design flow, but it opens the door for further leakage reduction when the MLV is not effective. We then present a divide-and-conquer approach that integrates gate replacement, an optimal MLV searching algorithm for tree circuits, and a genetic algorithm to connect the tree circuits. Our experimental results on all the MCNC91 benchmark circuits reveal that 1) the gate replacement technique alone can achieve 10% leakage current reduction over the best known IVC methods with no delay penalty and little area increase; 2) the divide-and-conquer approach outperforms the best pure IVC method by 24% and the existing control point insertion method by 12%; and 3) compared with the leakage achieved by optimal MLV in small circuits, the gate replacement heuristic and the divide-and-conquer approach can reduce on average 13% and 17% leakage, respectively.en
dc.format.extent595229 bytes
dc.format.mimetypeapplication/pdf
dc.identifier.citationL. Yuan and G. Qu. "A Combined Gate Replacement and Input Vector Control Approach for Leakage Current Reduction," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 14, No. 2, pp. 173-182, February 2006.en
dc.identifier.urihttp://hdl.handle.net/1903/8960
dc.language.isoen_USen
dc.publisherIEEEen
dc.relation.isAvailableAtA. James Clark School of Engineeringen_us
dc.relation.isAvailableAtElectrical & Computer Engineeringen_us
dc.relation.isAvailableAtDigital Repository at the University of Marylanden_us
dc.relation.isAvailableAtUniversity of Maryland (College Park, MD)en_us
dc.rights.licenseCopyright © 2006] IEEE. Reprinted from IEEE Transactions on Very Large Scale Integration (VLSI) Systems. This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of the University of Maryland's products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to pubs-permissions@ieee.org. By choosing to view this document, you agree to all provisions of the copyright laws protecting it.
dc.subjectGate replacementen
dc.subjectleakage reductionen
dc.subjectminimum leakage vector (MLV)en
dc.titleA Combined Gate Replacement and Input Vector Control Approach for Leakage Current Reductionen
dc.typeArticleen
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