High-Performance DRAMs in Workstation Environments
High-Performance DRAMs in Workstation Environments
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Date
2001-10
Authors
Cuppu, Vinodh
Jacob, Bruce
Davis, Brian
Mudge, Trevor
Advisor
Citation
"High performance DRAMs in workstation environments." Vinodh Cuppu, Bruce Jacob, Brian Davis, and Trevor Mudge. IEEE Transactions on Computers, vol. 50, no. 11, pp. 1133-1153. November 2001. (TC Special Issue on High-Performance Memory Systems)
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Abstract
This paper presents a simulation-based performance study of several of the new high-performance DRAM architectures, each evaluated in a small system organization. These small-system organizations correspond to workstation-class computers and use only a handful of DRAM chips (~10, as opposed to ~1 or ~100). The study covers Fast Page Mode, Extended Data Out, Synchronous, Enhanced Synchronous, Double Data Rate, Synchronous Link, Rambus, and Direct Rambus designs. Our simulations reveal several things: (a) current advanced DRAM technologies are attacking the memory bandwidth problem but not the latency problem; (b) bus transmission speed will soon become a primary factor limiting memory-system performance; (c) the post-L2 address stream still contains
significant locality, though it varies from application to application; (d) systems without L2 caches are feasible for low- and
medium-speed CPUs (1GHz and below); and (e) as we move to wider buses, row access time becomes more prominent, making it important to investigate techniques to exploit the available locality to decrease access time.