University of Maryland LibrariesDigital Repository at the University of Maryland
    • Login
    View Item 
    •   DRUM
    • A. James Clark School of Engineering
    • Electrical & Computer Engineering
    • Electrical & Computer Engineering Research Works
    • View Item
    •   DRUM
    • A. James Clark School of Engineering
    • Electrical & Computer Engineering
    • Electrical & Computer Engineering Research Works
    • View Item
    JavaScript is disabled for your browser. Some features of this site may not work without it.

    Synthesis Techniques for Low-Power Hard Real-Time Systems on Variable Voltage Processors

    Thumbnail
    View/Open
    c004.pdf (193.6Kb)
    No. of downloads: 870

    Date
    1998-12
    Author
    Hong, Inki
    Qu, Gang
    Potkonjak, Miodrag
    Srivastava, Mani B.
    Citation
    I. Hong, G. Qu, M. Potkonjak, and M.B. Srivastava.
    Metadata
    Show full item record
    Abstract
    The energy efficiency of systems-on-a-chip can be much improved if one were to vary the supply voltage dynamically at run time. In this paper we describe the synthesis of systems-on-a-chip based on core processors, while treating voltage (and correspondingly, the clock frequency) as a variable to be scheduled along with the computation tasks during the static scheduling step. In addition to describing the complete synthesis design flow for these variable voltage systems, we focus on the problem of doing the voltage scheduling while taking into account the inherent limitation on the rates at which the voltage and clock frequency can be changed by the power supply controllers and clock generators. Taking these limits on rate of change into account is crucial since changing the voltage by even a volt may take time equivalent to 100s to 10,000s of instructions on modern processors. We present both an exact but impractical formulation of this scheduling problem as a set of non-linear equations, as well as a heuristic approach based on reduction to an optimally solvable restricted ordered scheduling problem. Using various task mixes drawn from a set of nine real-life applications, our results show that we are able to reduce power consumption to within 7% of the lower bound obtained by imposing no limit at the rate of change of voltage and clock frequencies.
    URI
    http://hdl.handle.net/1903/9034
    Collections
    • Electrical & Computer Engineering Research Works
    Rights
    Copyright © 1998 IEEE. Reprinted from IEEE Real-Time Systems Symposium. This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of the University of Maryland's products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to pubs-permissions@ieee.org. By choosing to view this document, you agree to all provisions of the copyright laws protecting it.

    DRUM is brought to you by the University of Maryland Libraries
    University of Maryland, College Park, MD 20742-7011 (301)314-1328.
    Please send us your comments.
    Web Accessibility
     

     

    Browse

    All of DRUMCommunities & CollectionsBy Issue DateAuthorsTitlesSubjectsThis CollectionBy Issue DateAuthorsTitlesSubjects

    My Account

    LoginRegister
    Pages
    About DRUMAbout Download Statistics

    DRUM is brought to you by the University of Maryland Libraries
    University of Maryland, College Park, MD 20742-7011 (301)314-1328.
    Please send us your comments.
    Web Accessibility