Synthesis Techniques for Low-Power Hard Real-Time Systems on Variable Voltage Processors

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Date
1998-12Author
Hong, Inki
Qu, Gang
Potkonjak, Miodrag
Srivastava, Mani B.
Citation
I. Hong, G. Qu, M. Potkonjak, and M.B. Srivastava.
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Show full item recordAbstract
The energy efficiency of systems-on-a-chip can be much
improved if one were to vary the supply voltage dynamically
at run time. In this paper we describe the synthesis
of systems-on-a-chip based on core processors, while treating
voltage (and correspondingly, the clock frequency) as a
variable to be scheduled along with the computation tasks
during the static scheduling step. In addition to describing
the complete synthesis design flow for these variable
voltage systems, we focus on the problem of doing the voltage
scheduling while taking into account the inherent limitation
on the rates at which the voltage and clock frequency
can be changed by the power supply controllers and clock
generators. Taking these limits on rate of change into account
is crucial since changing the voltage by even a volt
may take time equivalent to 100s to 10,000s of instructions
on modern processors. We present both an exact but impractical
formulation of this scheduling problem as a set
of non-linear equations, as well as a heuristic approach
based on reduction to an optimally solvable restricted ordered
scheduling problem. Using various task mixes drawn
from a set of nine real-life applications, our results show
that we are able to reduce power consumption to within 7%
of the lower bound obtained by imposing no limit at the rate
of change of voltage and clock frequencies.