UMD Theses and Dissertations
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Item A BARE-DIE SIC-BASED ELECTRO-THERMALLY CO-DESIGNED WIRE-BONDLESS HIGH-FREQUENCY DC-DC CONVERTER(2021) Park, Yongwan; Khaligh, Alireza; Electrical Engineering; Digital Repository at the University of Maryland; University of Maryland (College Park, Md.)The current technological status of switch-mode power converters requires a paradigm shift to enable a substantial enhancement in power density. The emergence of wide-bandgap (WBG) devices such as Silicon Carbide (SiC) MOSFETs o↵ers the possibility to achieve high power-density by enabling higher switching frequency and higher temperature operation. This dissertation addresses the following shortcomings of conventional designs: 1) High values of commutation loop inductances and parasitic capacitances which prohibit fast, reliable and efficient switching performance, 2) inadequate thermal design capable of handling very high heat-fluxes (exceeding hundreds of W/cm2), which naturally stem from highly compact design and high allowable losses of the SiC devices, and 3) decoupled and sequential electrical and thermal designs, which leads to sub-optimal electro-thermal performance. As a solution to these challenges, this dissertation investigates two design strategies: 1) a novel switch module structure with low parasitics, and 2) a novel planar transformer structure with integrated leakage inductance and cooling system. Both approaches result in enhanced thermal performance, optimized through simultaneous electro-thermal co-design. A common key highlight of the proposed solutions is the high degree of integration realized by use of sub-components that integrate both electrical and thermal performance. This will save real estate by reducing component count and by lessening electrical and thermal burdens. In the first part of this dissertation, a detailed electrical characterization of a novel, wire-bondless, three-dimensional (3D), half-bridge switch module using bare-die SiC MOSFETs is presented. The switch assembly features the use of electro- thermally multi-functional components, simultaneously serving as bus-bars and heat sinks. A highly compact composition with embedded decoupling capacitors and gate driver components is realized with vertical loop structures for both power and gate drive circuits. Besides, the wire-bondless structure enables double-sided cooling, which significantly improves the thermal performance. 3D finite element analysis simulations and experiments demonstrate that the proposed switch module can achieve extremely low values of parasitic loop inductances (Lloop,power = 1.35 nH, Lloop,gate = 5.1 nH at a parasitic oscillation frequency of 100 MHz) as well as high thermal performance without entailing significant layout capacitances and resistances. The second part of this dissertation proposes an electro-thermal design optimization method of a high-frequency planar transformer with an integrated leakage inductance and thermal management system. Aiming at the use in a high-frequency (>500 kHz) dual-active-bridge (DAB) converter, an optimal leakage inductance selection process is explored based on highly accurate analyses of the DAB converter operation for maximizing the efficiency. Effect of design variables like the number of turns of the transformer and cooler height on the transformer’s electrical parameters such as leakage inductance, ac resistance and parasitic capacitance is further analyzed in detail. The dependence of converter efficiency on these parameters is estimated using realistic simulations and analyses, and potential trade-o↵s of the design are investigated. Thermal modeling is used to evaluate the thermal performance of different designs. Based on a combination of the analyses, optimal designs are identified, which simultaneously ensure good electrical and thermal performance. Finally, a compact DAB converter is designed based on the investigated components, operating at a switching frequency of 500 kHz. Robust gate-driver circuitry and auxiliary parts are also developed to tolerate such high switching frequency as well as high dv/dt. The optimal design processes, operation strategies and analytical models are validated through diverse experiments on 3.3 kW dc-dc converter operation. As a result of the investigations, the converter achieves zero-voltage-switching over various load conditions with satisfactory high-frequency waveforms and a peak efficiency of 98%. The converter’s operation at high power is validated through a designed loss-emulation test corresponding to 8.4 kW operation.Item DFT AND RELATED MODELING OF POST-SILICON VALENCE 4 MATERIALS: SiC AND Ge(2020) Darmody, Christopher; Goldsman, Neil; Electrical Engineering; Digital Repository at the University of Maryland; University of Maryland (College Park, Md.)Though silicon (Si) is in many ways the material of choice for many electronic applications due in part to its mature processing technology, its intrinsic properties are not always suited for every challenge. Specialized high power and high temper- ature devices benefit from using semiconductors with a larger band-gap and higher thermal conductivity such as silicon carbide (SiC). Additionally, the 1.1eV bandgap of Si makes it unable to effectively absorb infrared photons so a material with a smaller bandgap, like germanium (Ge), is more suited to the task. Currently SiC power transistors are commercially available but suffer from poor channel mobility due to interface roughness which limits their performance. To predict the maximum theoretically achievable mobility for different crystallo- graphic interfaces I developed a novel technique for extracting an atomic-roughness scattering rate from an arbitrary atomic surface. The term atomic-roughness here means an interface purely due to the variation of atom species and position without the presence of a crystallographic miscut due to epitaxial growth considerations. I used Density Functional Theory (DFT) to obtain a perturbation potential from which I can calculate a scattering rate. This scattering rate can then be used in a Monte Carlo simulation to predict mobility for a given field configuration. In addition to SiC’s low channel mobility, SiC p-type dopant species also ex- hibit an abnormally large ionization energy compared to its n-type dopants and to the primary dopants in many other semiconductors. This fact can cause is- sues such as unexpectedly high resistance regions at lower operating temperatures - causing the need to dope at significantly higher concentration. To characterize the incomplete ionization fraction p/N A , I first gathered nearly all existing pub- lished data on the ionization energy of aluminum (Al) in 4H-SiC and created an empirical concentration-dependent model of this function. Then I put together a physics-based model of the entire acceptor and valence band system and used my concentration-dependent ionization energy as an input to predict p/N A . I verify my physics-based model result against a separate experimental dataset derived from nearly-exhaustive literature measurements of Hall mobility and resistivity. Finally, I transform fully temperature-dependent result of p/N A from a complex numerical computation to a more easily implementable parameterized function with the use of a genetic algorithm. The remaining part of my work was performed on Germanium which has interesting application in short-wave infrared imaging due its 0.66eV indirect and 0.85 eV direct bandgaps, which corresponds closely to the peak illumination of the “night glow” at 0.75 eV. Optical devices greatly benefit from direct gap band structures to increase photon absorption and emission efficiency. Though Ge is an indirect gap material, it can be alloyed with a direct gap material, namely tin (Sn), to transition it to a direct gap material at a certain molar fraction. Through DFT calculations I investigate the nature of this transition and determine theoretically the minimum molar fraction needed to achieve a direct bandgap.Item INTEGRATED MODELING OF RELIABILITY AND PERFORMANCE OF 4H-SILICON CARBIDE POWER MOSFETS USING ATOMISTIC AND DEVICE SIMULATIONS(2015) Perinthatta Ettisserry, Devanarayanan; Goldsman, Neil; Electrical Engineering; Digital Repository at the University of Maryland; University of Maryland (College Park, Md.)4H-Silicon Carbide (4H-SiC) power MOSFET is a promising technology for future high-temperature and high-power electronics. However, poor device reliability and performance, that stem from the inferior quality of 4H-SiC/SiO2 interface, have hindered its development. This dissertation investigates the role of interfacial and near-interfacial atomic defects as the root cause of these key concerns. Additionally, it explores device processing strategies for mitigating reliability-limiting defects. In order to understand the atomic nature of material defects, and their manifestations in electrical measurements, this work employs an integrated modeling approach together with experiments. Here, the electronic and structural properties of defects are analyzed using first-principles hybrid Density Functional Theory (DFT). The insights from first-principles calculations are integrated with conventional physics-based modeling techniques like Drift-Diffusion and Rate equation simulations to model various device characteristics. Subsequently, the atomic-level models are validated by comparison with experiments. From device reliability perspective, this dissertation models the time-dependent worsening of threshold voltage (Vth) instability in 4H-SiC MOSFETs operated under High-Temperature and Gate-Bias (HTGB) conditions. It proposes a DFT-based oxygen-vacancy hole trap activation model, where certain originally ‘electrically inactive’ oxygen vacancies are structurally transformed under HTGB stress to form electrically ‘active’ switching oxide hole traps. The transients of this atomistic process were simulated with inputs from DFT. The calculated time-evolution of the buildup of positively charged vacancies correlated well with the experimentally measured time-dependence of HTGB-induced Vth instability. Moreover, this work designates near-interfacial single carbon interstitial defect in SiO2 as an additional switching oxide hole trap that could cause room-temperature Vth instability. This work employs DFT-based molecular dynamics to develop device processing strategies that could mitigate reliability-limiting defects in 4H-SiC MOSFETs. It identifies Fluorine treatment to be effective in neutralizing oxygen vacancy and carbon-related hole traps, unlike molecular hydrogen. Similarly, Nitric Oxide passivation is found to eliminate carbon-related defects. From device performance perspective, this dissertation proposes a methodology to identify and quantify channel mobility-limiting interfacial defects by integrating Drift-Diffusion simulations of 4H-SiC power MOSFET with DFT. It identifies the density of interface trap spectrum to be composed of three atomically distinct defects, one of which is potentially carbon di-interstitial defect.Item Kelvin Probe Microscopy Studies of Epitaxial Graphene on SiC(0001)(2011) Curtin, Alexandra E.; Fuhrer, Michael S; Physics; Digital Repository at the University of Maryland; University of Maryland (College Park, Md.)Epitaxial graphene on SiC(0001) presents a promising platform for device applications and fundamental investigations. Graphene growth on SiC(0001) can produce consistent monolayer thickness on terraces and good electronic properties. In exfoliated graphene on SiO2, random charged impurities in the SiO2 surface are thought to be the dominant scatterers, explaining the observed transport properties as well as the spatial charge inhomogeneity seen in scanned-probe experiments. In contrast, the scattering mechanisms and charge distribution in epitaxial graphene remain relatively unexplored. Here I use Kelvin probe microscopy (KPM) in ambient and UHV conditions to directly measure the surface potential of epitaxial graphene on SiC(0001). Ambient-environment KPM on graphene/SiC(0001) shows surface potential variations of only 12 meV. Taken together with transport measurements, the data suggest that the graphene samples in ambient are in the low-doped regime, near the minimum conductivity of roughly 4e2/h. I am also able to use UHV KPM of graphene/ SiC(0001) to identify the discrete surface potentials of monolayer and bilayer graphene as well as the insulating interfacial carbon layer and bare SiC, correlated with scanning electron micrographs of the same location. The surface potential differences between monolayer and bilayer graphene and between IFL and monolayer graphene are both suggestive of low doping (≤1012 cm-2). The surface potentials of monolayer and bilayer graphene are relatively smooth, while the IFL and bare SiC, in contrast, showed larger variations in surface potential suggesting the presence of unscreened charged impurities present on the IFL that are later screened by the overgrown graphene. I model the potential variations for unscreened and graphene-screened charged impurities using the self-consistent theory of graphene developed by Adam et al. The results show that although surface potential variations are, as expected, larger in the IFL than in graphene, both surfaces display surface potential variations 10-40 times smaller than predicted by theory. While ambient electronic transport data and surface potential steps suggest our samples are only lightly doped (≤1012 cm-2), in a regime dominated by electron-hole puddles, we do not observe these puddles in UHV. The absence of puddles in UHV leaves the source of doping in these samples an open question.Item Cause and Effect of Threshold-Voltage Instability on the Reliability of Silicon-Carbide MOSFETs(2011) Lelis, Aivars J.; Goldsman, Neil; Reliability Engineering; Digital Repository at the University of Maryland; University of Maryland (College Park, Md.)A significant instability of the threshold voltage (VT) in silicon carbide (SiC) MOSFETs in response to gate-bias and ON-state current stressing was discovered and examined as a function of bias, temperature, and time. It was determined that the likely mechanism causing this effect is the charging and discharging of gate-oxide traps, located close to the interface of the SiC conducting channel, via a direct tunneling mechanism. High-temperature reverse-bias induced leakage current in the OFF-state was identified as a potential failure mode. A simultaneous two-way tunneling model was developed, based on an existing one-way tunneling model, to simulate the time-dependent and field-dependent charging and discharging of the near-interfacial oxide traps in response to an applied gate-bias stress. The simulations successfully matched experimental results, both with respect to measurement time and to bias-stress time as a function of gate bias. Experimental results were presented, showing that the VT instability increases with both increasing gate-bias-stress time and bias-stress magnitude. The measurement conditions, including gate-ramp speed and direction, were shown to have a significant influence on the measured result, with a 20-μs measurement revealing instabilities three times greater than those at standard 1-s measurement speeds, whereas 1-ks measurements showed shifts only half as large. High-temperature bias stressing was found to cause even more significant increases in the VT instability. ON-state current stressing was found to also increase the VT instability, due to self-heating effects. VT shifts as large as 2 V were reported, with the number of calculated oxide traps switching charge state varying between 1×1011 and 8×1011 cm–2, depending on processing, stress, and measurement conditions. The standard post-oxidation NO anneal was shown to reduce the number of active oxide traps by about 70 percent. The dominant oxide trap was identified as an E-prime-center type defect—a weak Si-Si bond due to an oxygen vacancy which has been broken during processing or subsequent device stressing. The large increase in bias-stress induced VT instability at temperatures above 100 °C was explained by an increase in the number of active E-prime-center type defects. Existing reliability qualification standards based on silicon device technology are inadequate for SiC MOSFETs and need to be revised, with particular attention paid to the measurement conditions.Item Modeling and Characterization of 4H-SIC MOSFETs: High Field, High Temperature, and Transient Effects(2008-11-21) Potbhare, Siddharth; Goldsman, Neil; Electrical Engineering; Digital Repository at the University of Maryland; University of Maryland (College Park, Md.)We present detailed physics based numerical models for characterizing 4H-Silicon Carbide lateral MOSFETs and vertical power DMOSFETs for high temperature, high field, DC, AC and transient switching operating conditions. A complete 2-D Drift-Diffusion based device simulator has been developed specifically for SiC MOSFETs, to evaluate device performance in a variety of operating scenarios, and to extract relevant physical parameters. We have developed and implemented room and high temperature mobility models for bulk phonon and impurity scattering, surface phonon scattering, Coulomb scattering from interface traps, and surface roughness scattering. High temperature models for interface trap density of states and occupation probability of interface traps are also implemented. By rigorous comparison of simulated I-V characteristics to experimental data at high temperatures, physical parameters like interface trap density of states, surface step height, saturation velocity, etc. have been extracted. Insight into relative importance of scattering mechanisms influencing transport in SiC MOSFETs has been provided. We show that the strongest contribution to low current in SiC MOSFETs is from the loss of mobile inversion charge due to large amount of trapping at the interface, and due to very low surface mobility arising due to a rough SiC-SiO2 interface. We show that surface roughness scattering dominates at high gate biases and is the most important scattering mechanism in 4H-SiC MOSFETs. Switching characteristics of SiC lateral MOSFETs have been modeled and simulated using our custom device simulator. A comprehensive generation-recombination model for interaction between inversion layer electrons and interface traps has been developed. Using this model, we have modeled the time-dependent occupation of interface traps spread inside the SiC bandgap. We have measured the transient characteristics of these devices, and compare our simulation to experiment and have extracted capture cross-sections of interface traps. Using the coupled experiment and modeling approach, we are able to distinguish between fast interface traps and slow oxide traps, and explain how they contribute to threshold voltage instability. High power 4H-SiC DMOSFET operation in the ON and the OFF states has also been analyzed. We show that in current generation SiC DMOSFETs, the ON resistance is dominated by the channel resistance instead of the drift-layer resistance. This makes the design of SiC DMOSFETs far from ideal. OFF state blocking capability and breakdown due to impact ionization of the DMOSFETs are also modeled and simulated. We show that the 4H-SiC DMOSFETs have excellent leakage characteristics and can support extremely high OFF state drain voltages.Item Characterization of 4H-SiC MOSFETs Using First Principles Coulomb Scattering Mobility Modeling and Device Simulation(2005-12-01) Potbhare, Siddharth; Goldsman, Neil; Electrical Engineering; Digital Repository at the University of Maryland; University of Maryland (College Park, Md.)Detailed analysis of a 4H-SiC MOSFET has been carried out by numerically solving the steady state semiconductor Drift-Diffusion equations. Mobility models for bulk phonon scattering, surface phonon scattering, surface roughness scattering, Coulomb scattering by interface traps and oxide charges, and high field effects, have been developed and implemented. A first principles Coulomb scattering mobility model has been developed specifically to model the physics of the inversion layer in 4H-SiC MOSFETs. The Coulomb scattering model takes into account, scattering of mobile charges by occupied interface traps and fixed oxide charges, distribution of mobile charges in the inversion layer, and screening. Simulated IV curves have been compared to experimental data. Density of states for the interface traps have been extracted, and seem to be in agreement with experimental measurements. Simulations indicate that occupied interface traps in 4H-SiC MOSFETs are responsible for mobility degradation, low currents and high threshold voltages. Their effect diminishes at high temperatures due to reduction in trap occupancy, and at high gate voltages due to increased screening. At high gate voltages, surface roughness scattering plays the major role in mobility degradation in 4H-SiC MOSFETs.