Cause and Effect of Threshold-Voltage Instability on the Reliability of Silicon-Carbide MOSFETs

Abstract

A significant instability of the threshold voltage (VT) in silicon carbide (SiC) MOSFETs in response to gate-bias and ON-state current stressing was discovered and examined as a function of bias, temperature, and time. It was determined that the likely mechanism causing this effect is the charging and discharging of gate-oxide traps, located close to the interface of the SiC conducting channel, via a direct tunneling mechanism. High-temperature reverse-bias induced leakage current in the OFF-state was identified as a potential failure mode. A simultaneous two-way tunneling model was developed, based on an existing one-way tunneling model, to simulate the time-dependent and field-dependent charging and discharging of the near-interfacial oxide traps in response to an applied gate-bias stress. The simulations successfully matched experimental results, both with respect to measurement time and to bias-stress time as a function of gate bias. Experimental results were presented, showing that the VT instability increases with both increasing gate-bias-stress time and bias-stress magnitude. The measurement conditions, including gate-ramp speed and direction, were shown to have a significant influence on the measured result, with a 20-μs measurement revealing instabilities three times greater than those at standard 1-s measurement speeds, whereas 1-ks measurements showed shifts only half as large. High-temperature bias stressing was found to cause even more significant increases in the VT instability. ON-state current stressing was found to also increase the VT instability, due to self-heating effects. VT shifts as large as 2 V were reported, with the number of calculated oxide traps switching charge state varying between 1×1011 and 8×1011 cm–2, depending on processing, stress, and measurement conditions. The standard post-oxidation NO anneal was shown to reduce the number of active oxide traps by about 70 percent. The dominant oxide trap was identified as an E-prime-center type defect—a weak Si-Si bond due to an oxygen vacancy which has been broken during processing or subsequent device stressing. The large increase in bias-stress induced VT instability at temperatures above 100 °C was explained by an increase in the number of active E-prime-center type defects. Existing reliability qualification standards based on silicon device technology are inadequate for SiC MOSFETs and need to be revised, with particular attention paid to the measurement conditions.