Electrical & Computer Engineering Theses and Dissertations

Permanent URI for this collectionhttp://hdl.handle.net/1903/2765

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    A VLSI Design for Phase Synchronization of Two Globally Coupled Oscillators
    (2017) Luo, Hua; Newcomb, Robert W.; Electrical Engineering; Digital Repository at the University of Maryland; University of Maryland (College Park, Md.)
    Phase synchronization of globally coupled oscillators is a common phenomenon in almost every branch of science including chemistry, physics, astronomy, biology, and electronics. It has various applications such as laser arrays, chemical and electrical oscillators, metronomes, pathological synchronization in Parkinson’s disease, and synchronized oscillation of neurons. In this thesis, we study and design globally coupled oscillators with a focus on biological applications. We mathematically analyze one of the most widely studied models of globally coupled oscillators proposed by Matthews et al.. Based on this model, we design two globally coupled oscillator systems in Simulink. Simulation results show that our systems work perfectly as synchronized globally coupled oscillators. We then design a two-channel globally coupled oscillator system with integrated circuits using ON Semiconductor’s 0.5 µm CMOS technology and a ±5 V power supply. Simulation results in PSpice show that the two channels get synchronized in less than one cycle and they can oscillate at frequencies less than 1 Hz.
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    ENABLING HARDWARE TECHNOLOGIES FOR AUTONOMY IN TINY ROBOTS: CONTROL, INTEGRATION, ACTUATION
    (2016) Lee, Tsung-Hsueh; Abshire, Pamela A; Electrical Engineering; Digital Repository at the University of Maryland; University of Maryland (College Park, Md.)
    The last two decades have seen many exciting examples of tiny robots from a few cm3 to less than one cm3. Although individually limited, a large group of these robots has the potential to work cooperatively and accomplish complex tasks. Two examples from nature that exhibit this type of cooperation are ant and bee colonies. They have the potential to assist in applications like search and rescue, military scouting, infrastructure and equipment monitoring, nano-manufacture, and possibly medicine. Most of these applications require the high level of autonomy that has been demonstrated by large robotic platforms, such as the iRobot and Honda ASIMO. However, when robot size shrinks down, current approaches to achieve the necessary functions are no longer valid. This work focused on challenges associated with the electronics and fabrication. We addressed three major technical hurdles inherent to current approaches: 1) difficulty of compact integration; 2) need for real-time and power-efficient computations; 3) unavailability of commercial tiny actuators and motion mechanisms. The aim of this work was to provide enabling hardware technologies to achieve autonomy in tiny robots. We proposed a decentralized application-specific integrated circuit (ASIC) where each component is responsible for its own operation and autonomy to the greatest extent possible. The ASIC consists of electronics modules for the fundamental functions required to fulfill the desired autonomy: actuation, control, power supply, and sensing. The actuators and mechanisms could potentially be post-fabricated on the ASIC directly. This design makes for a modular architecture. The following components were shown to work in physical implementations or simulations: 1) a tunable motion controller for ultralow frequency actuation; 2) a nonvolatile memory and programming circuit to achieve automatic and one-time programming; 3) a high-voltage circuit with the highest reported breakdown voltage in standard 0.5 μm CMOS; 4) thermal actuators fabricated using CMOS compatible process; 5) a low-power mixed-signal computational architecture for robotic dynamics simulator; 6) a frequency-boost technique to achieve low jitter in ring oscillators. These contributions will be generally enabling for other systems with strict size and power constraints such as wireless sensor nodes.
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    INTEGRATION OF CMOS TECHNOLOGY INTO LAB-ON-CHIP SYSTEMS APPLIED TO THE DEVELOPMENT OF A BIOELECTRONIC NOSE
    (2015) Datta-Chaudhuri, Timir Baran; Abshire, Pamela A; Electrical Engineering; Digital Repository at the University of Maryland; University of Maryland (College Park, Md.)
    This work addresses the development of a lab-on-a-chip (LOC) system for olfactory sensing. The method of sensing employed is cell-based, utilizing living cells to sense stimuli that are otherwise not easily sensed using conventional transduction techniques. Cells have evolved over millions of years to be exquisitely sensitive to their environment, with certain types of cells producing electrical signals in response to stimuli. The core device that is introduced here is comprised of living olfactory sensory neurons (OSNs) on top of a complementary metal-oxide-semiconductor (CMOS) integrated circuit (IC). This hybrid bioelectronic approach to sensing leverages the sensitivity of OSNs with the electronic signal processing capability of modern ICs. Intimately combining electronics with biology presents a number of unique challenges to integration that arise from the disparate requirements of the two separate domains. Fundamentally the obstacles arise from the facts that electronic devices are designed to work in dry environments while biology requires not only a wet environment, but also one that is precisely controlled and non-toxic. Design and modeling of such heterogeneously integrated systems is complicated by the lack of tools that can address the multiple domains and techniques required for integration, namely IC design, fluidics, packaging, and microfabrication, and cell culture. There also arises the issue of how to handle the vast amount of data that can be generated by such systems, and specifically how to efficiently identify signals of interest and communicate them off-chip. The primary contributions of this work are the development of a new packaging scheme for integration of CMOS ICs into fluidic LOC systems, a methodology for cross-coupled multi-domain iterative modeling of heterogeneously integrated systems, demonstration of a proof-of-concept bioelectronic olfactory sensor, and a novel event-based technique to minimize the bandwidth required to communicate the information contained in bio-potential signals produced by dense arrays of electrically active cells.
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    CMOS IMAGE SENSORS FOR LAB-ON-A-CHIP MICROSYSTEM DESIGN
    (2011) Sander, David; Abshire, Pamela; Electrical Engineering; Digital Repository at the University of Maryland; University of Maryland (College Park, Md.)
    The work described herein serves as a foundation for the development of CMOS imaging in lab-on-a-chip microsystems. Lab-on-a-chip (LOC) systems attempt to emulate the functionality of a cell biology lab by incorporating multiple sensing modalidites into a single microscale system. LOC are applicable to drug development, implantable sensors, cell-based bio-chemical detectors and radiation detectors. The common theme across these systems is achieving performance under severe resource constraints including noise, bandwidth, power and size. The contributions of this work are in the areas of two core lab-on-a-chip imaging functions: object detection and optical measurements.
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    Characterization and Modeling of High Power Microwave Effects in CMOS Microelectronics
    (2010) Holloway, Michael Andrew; O'Shea, Patrick G; Electrical Engineering; Digital Repository at the University of Maryland; University of Maryland (College Park, Md.)
    The intentional use of high power microwave (HPM) signals to disrupt microelectronic systems is a substantial threat to vital infrastructure. Conventional methods to assess HPM threats involve empirical testing of electronic equipment, which provides no insight into fundamental mechanisms of HPM induced upset. The work presented in this dissertation is part of a broad effort to develop more effective means for HPM threat assessment. Comprehensive experimental evaluation of CMOS digital electronics was performed to provide critical information of the elementary mechanisms that govern the dynamics of HPM effects. Results show that electrostatic discharge (ESD) protection devices play a significant role in the behavior of circuits irradiated by HPM pulses. The PN junctions of the ESD protection devices distort HPM waveforms producing DC voltages at the input of the core logic elements, which produces output bit errors and abnormal circuit power dissipation. The dynamic capacitance of these devices combines with linear parasitic elements to create resonant structures that produce nonlinear circuit dynamics such as spurious oscillations. The insight into the fundamental mechanisms this research has revealed will contribute substantially to the broader effort aimed at identifying and mitigating susceptibilities in critical systems. Also presented in this work is a modeling technique based on scalable analytical circuit models that accounts for the non-quasi-static behavior of the ESD protection PN junctions. The results of circuit simulations employing these device models are in excellent agreement with experimental measurements, and are capable of predicting the threshold of effect for HPM driven non-linear circuit dynamics. For the first time, a deterministic method of evaluating HPM effects based on physical, scalable device parameters has been demonstrated. The modeling presented in this dissertation can be easily integrated into design cycles and will greatly aid the development of electronic systems with improved HPM immunity.
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    CMOS N-Dimensional M-Level Hysteresis Circuits and Possible Applications
    (2007-11-27) Jiang, Yu; Newcomb, Robert W; Electrical Engineering; Digital Repository at the University of Maryland; University of Maryland (College Park, Md.)
    Hysteresis is a natural phenomenon existing in many systems. Binary hysteresis is the simplest yet important model to study electronically generated hysteresis. Binary hysteresis circuits, the Schmitt trigger being an example, are widely used in reducing noise sensitivity, designing oscillators, generating chaotic signals, etc. A new concept, n-dimensional m-level multi-cell hysteresis is presented. A group of CMOS binary hysteresis circuits with full control which operate in all four quadrants is introduced. CMOS circuits, that give various one-dimensional multi-level hysteresis, in both current mode and voltage mode, are presented. Various combinations of adding forward and reverse binary hysteresis are demonstrated. CMOS circuits, in both current mode and voltage mode, that give two-dimensional multi-level multicell hysteresis, are designed. Further discussion is given on how to extend the results to more dimensions. Two-dimensional hysteresis is used to generate chaotic signals. A couple of areas where multi-cell hysteresis can be useful are suggested.
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    DESIGN AND FABRICATION OF ON CHIP MICROWAVE PULSE POWER DETECTORS
    (2005-12-05) Jeon, Woochul; MELNGAILIS, JOHN; Electrical Engineering; Digital Repository at the University of Maryland; University of Maryland (College Park, Md.)
    On-chip microwave pulse-power detectors are promising devices for many electrical systems of both military and commercial applications. Most research in microwave power detector design have been focused on thermal power detectors, such as thermistors or thermocouples, due to their wide dynamic range and high frequency operation. However, due to their slow thermal response time, it is impossible to detect microwave pulses with a few micro or sub-micro seconds of pulse width. Schottky diode power detectors are the best candidates for this purpose due to their fast pulse response time and small size. We have developed a means for fabricating Schottky diodes as part of any Complementary-Metal-Oxide-Semiconductor (CMOS) process by modifying the layout file. CMOS Schottky diodes were added at pre-selected locations through a CMOS process. We have also developed a process for adding or deleting Schottky diodes on a CMOS fabricated chip by using Focused Ion Beam (FIB). FIB milling and ion induced deposition were used for adding or deleting Schottky diodes at any desired location on a CMOS-fabricated chip as a post-CMOS process. Spice models of CMOS Schottky diodes were developed and used for designing the RF front end circuits in passive RF circuits. MOSFET based RF pulsed power detector circuits were also designed and fabricated. Fabricated power detectors were tested under direct injection and radiation of microwave pulse signals. Measured results for fabricated CMOS Schottky diodes, FIB Schottky diodes and MOSFET half-wave and full-wave rectifier circuits are summarized in a table with the pulse response time, the dynamic range, the sensitivity, and the frequency response to determine which power detector is the best choice for detecting a specific source signal.