CMOS N-Dimensional M-Level Hysteresis Circuits and Possible Applications

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2007-11-27

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Abstract

Hysteresis is a natural phenomenon existing in many systems. Binary hysteresis is the simplest yet important model to study electronically generated hysteresis. Binary hysteresis circuits, the Schmitt trigger being an example, are widely used in reducing noise sensitivity, designing oscillators, generating chaotic signals, etc. A new concept, n-dimensional m-level multi-cell hysteresis is presented. A group of CMOS binary hysteresis circuits with full control which operate in all four quadrants is introduced. CMOS circuits, that give various one-dimensional multi-level hysteresis, in both current mode and voltage mode, are presented. Various combinations of adding forward and reverse binary hysteresis are demonstrated. CMOS circuits, in both current mode and voltage mode, that give two-dimensional multi-level multicell hysteresis, are designed. Further discussion is given on how to extend the results to more dimensions. Two-dimensional hysteresis is used to generate chaotic signals. A couple of areas where multi-cell hysteresis can be useful are suggested.

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