Optimal Systolic Designs for the Computation of the Discrete Hartley and the Discrete Cosine Transforms.

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dc.contributor.authorChakrabarti, Chaitalien_US
dc.contributor.authorJaJa, Joseph F.en_US
dc.contributor.departmentISRen_US
dc.date.accessioned2007-05-23T09:41:04Z
dc.date.available2007-05-23T09:41:04Z
dc.date.issued1988en_US
dc.description.abstractIn this paper, we propose new algorithms for computing the Discrete Hartley and the Discrete Cosine Transform. The algorithms are based on iterative applications of the mod)fied small n algorithms of DFT. The one dimensional transforms are mapped into two dimensions first and then implemented on two dimensional systolic arrays. Pipelined bit serial architectures operating on left to right LSB to MSB binary arithmetic is the basis of the hardware design. Different hardware schemes for implementing these transforms are studied. We show that our schemes achieve a substantial speed-up over existing schemes.en_US
dc.format.extent1214396 bytes
dc.format.mimetypeapplication/pdf
dc.identifier.urihttp://hdl.handle.net/1903/4758
dc.language.isoen_USen_US
dc.relation.ispartofseriesISR; TR 1988-26en_US
dc.titleOptimal Systolic Designs for the Computation of the Discrete Hartley and the Discrete Cosine Transforms.en_US
dc.typeTechnical Reporten_US

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