VLSI CAD Tool Protection by Birthmarking Design Solutions

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dc.contributor.authorYuan, Lin
dc.contributor.authorQu, Gang
dc.contributor.authorSrivastava, Ankur
dc.date.accessioned2009-05-11T13:54:12Z
dc.date.available2009-05-11T13:54:12Z
dc.date.issued2005-04
dc.description.abstractMany techniques have been proposed in the past for the protection of VLSI design IPs (intellectual property). CAD tools and algorithms are intensively used in all phases of modern VLSI designs; however, little has been done to protect them. Basically, given a problem P and a solution S, we want to be able to determine whether S is obtained by a particular tool or algorithm. We propose two techniques that intentionally leave some trace or birthmark, which refers to certain easy detectable properties, in the design solutions to facilitate CAD tool tracing and protection. The pre-processing technique provides the ideal protection at the cost of losing control of solution’s quality. The post-processing technique balances the level of protection and design quality. We conduct a case study on how to protect a timing-driven gate duplication algorithm. Experimental results on a large set of MCNC benchmarks confirm that the pre-processing technique results in a significant reduction (about 48%) of the optimization power of the tool, while the post-processing technique has almost no penalty (less than 2%) on the tool’s performance.en
dc.format.extent53378 bytes
dc.format.mimetypeapplication/pdf
dc.identifier.citationL. Yuan, G. Qu, and A. Srivastava. "VLSI CAD Tool Protection by Birthmarking Design Solutions," 15th IEEE /ACM Great Lakes Symposium on VLSI (GLSVLSI'05), pp. 341-344, April 2005.en
dc.identifier.urihttp://hdl.handle.net/1903/9068
dc.language.isoen_USen
dc.publisherIEEEen
dc.relation.isAvailableAtA. James Clark School of Engineeringen_us
dc.relation.isAvailableAtElectrical & Computer Engineeringen_us
dc.relation.isAvailableAtDigital Repository at the University of Marylanden_us
dc.relation.isAvailableAtUniversity of Maryland (College Park, MD)en_us
dc.rights.licenseCopyright © 2005 IEEE. Reprinted from 15th IEEE/ACM Great Lakes Symposium on VLSI. This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of the University of Maryland's products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to pubs-permissions@ieee.org. By choosing to view this document, you agree to all provisions of the copyright laws protecting it.
dc.subjectCADen
dc.subjectprotectionen
dc.subjectbirthmarkingen
dc.subjectintellectual propertyen
dc.titleVLSI CAD Tool Protection by Birthmarking Design Solutionsen
dc.typeArticleen

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