VLSI Design of Discrete Fourier Transform Processors
VLSI Design of Discrete Fourier Transform Processors
Loading...
Files
Publication or External Link
Date
1991
Authors
Advisor
Citation
DRUM DOI
Abstract
A bit-serial cell library is presented which can been used to rapidly implement discrete Fourier transform algorithms in VLSI circuit technology. The design methodology employs systolic summation arrays and multiplier arrays which are bit-serial and fully pipelined. To demonstrate the utility and performance of this cell library, an 8-point discrete Fourier transform (DFT) processor has been designed and implemented as a VLSI chip which at 50 MHz and has a throughput of 2.9 million complex 8-point 16- bit DFT's per second.