VLSI Design of Discrete Fourier Transform Processors

dc.contributor.advisor	JaJa, Joseph F.	en_US
dc.contributor.author	Goodrich, Todd A.	en_US
dc.contributor.department	ISR	en_US
dc.date.accessioned	2007-05-23T09:49:36Z
dc.date.available	2007-05-23T09:49:36Z
dc.date.issued	1991	en_US
dc.description.abstract	A bit-serial cell library is presented which can been used to rapidly implement discrete Fourier transform algorithms in VLSI circuit technology. The design methodology employs systolic summation arrays and multiplier arrays which are bit-serial and fully pipelined. To demonstrate the utility and performance of this cell library, an 8-point discrete Fourier transform (DFT) processor has been designed and implemented as a VLSI chip which at 50 MHz and has a throughput of 2.9 million complex 8-point 16- bit DFT's per second.	en_US
dc.format.extent	3444840 bytes
dc.format.mimetype	application/pdf
dc.identifier.uri	http://hdl.handle.net/1903/5174
dc.language.iso	en_US	en_US
dc.relation.ispartofseries	ISR; MS 1991-3	en_US
dc.subject	distributed information processing	en_US
dc.subject	filtering	en_US
dc.subject	image processing	en_US
dc.subject	signal processing	en_US
dc.subject	speech processing	en_US
dc.subject	algorithms	en_US
dc.subject	computational geometry	en_US
dc.subject	parallel architectures	en_US
dc.subject	VLSI architectures	en_US
dc.subject	computer aided design	en_US
dc.subject	automation	en_US
dc.subject	Systems Integration	en_US
dc.title	VLSI Design of Discrete Fourier Transform Processors	en_US
dc.type	Thesis	en_US

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