Power Optimization of Variable-Voltage Core-Based Systems

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Date
1998-06Author
Hong, Inki
Kirovski, Darko
Qu, Gang
Potkonjak, Miodrag
Srivastava, Mani B.
Citation
I. Hong, D. Kirovski, G. Qu, M. Potkonjak, and M. Srivastava. "Power Optimization of Variable Voltage Core-Based Systems," 35th ACM/IEEE Design Automation Conference Proceedings, pp. 176-181, June 1998.
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Show full item recordAbstract
The growing class of portable systems, such as
personal computing and communication devices, has resulted in a
new set of system design requirements, mainly characterized by
dominant importance of power minimization and design reuse.
The energy efficiency of systems-on-a-chip (SOC) could be much
improved if one were to vary the supply voltage dynamically
at run time. We develop the design methodology for the lowpower
core-based real-time SOC based on dynamically variable
voltage hardware. The key challenge is to develop effective
scheduling techniques that treat voltage as a variable to be
determined, in addition to the conventional task scheduling and
allocation. Our synthesis technique also addresses the selection of
the processor core and the determination of the instruction and
data cache size and configuration so as to fully exploit dynamically
variable voltage hardware, which results in significantly
lower power consumption for a set of target applications than
existing techniques. The highlight of the proposed approach is
the nonpreemptive scheduling heuristic, which results in solutions
very close to optimal ones for many test cases. The effectiveness of
the approach is demonstrated on a variety of modern industrial-strength
multimedia and communication applications.