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dc.contributor.advisorJaJa, Joseph F.en_US
dc.contributor.authorChakrabarti, Chaitalien_US
dc.date.accessioned2007-05-23T09:46:45Z
dc.date.available2007-05-23T09:46:45Z
dc.date.issued1990en_US
dc.identifier.urihttp://hdl.handle.net/1903/5032
dc.description.abstractMany real-time signal processing tasks require the ability to process very large amounts of data at very high throughput rates. In this report we present efficient special-purpose VLSI architectures for computing several real-time signal processing tasks including one dimensional Discrete Hartley (DHT) and Discrete Cosine transforms (DCT), multi-dimensional transforms, template matching and block matching.<P>We first develop completely pipelined bit-serial systolic array architectures for computing one-dimensional DHT and DCT, when the number of sample points N is factorizable into mutually prime factors N1 and N2. We then develop a family of {em optimal} (as defined by VLSI complexity theory) architectures with area-time trade-offs for computing any (NxNx...xN) d-dimensional linear separable transforms. Finally we present semi-systolic linear array architectures for computing template matching and block matching, that are capable of handling the computations as well as the I/O bandwidth requirements efficiently.<P>en_US
dc.format.extent4655486 bytes
dc.format.mimetypeapplication/pdf
dc.language.isoen_USen_US
dc.relation.ispartofseriesISR; PhD 1990-6en_US
dc.subjectparallel architecturesen_US
dc.subjectVLSI architecturesen_US
dc.subjectSystems Integrationen_US
dc.titleVLSI Architectures for Real-Time Signal Processingen_US
dc.typeDissertationen_US
dc.contributor.departmentISRen_US


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