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VLSI Architectures Based on the Small N Algorithms.

dc.contributor.authorJaJa, Joseph F.en_US
dc.contributor.authorOwens, R.M.en_US
dc.date.accessioned2007-05-23T09:33:58Z
dc.date.available2007-05-23T09:33:58Z
dc.date.issued1985en_US
dc.identifier.urihttp://hdl.handle.net/1903/4384
dc.description.abstractDigital convolution and the discrete Fourier transform are basic operations whose computational requirements are of great importance in many applications. In this paper, we propose new types of VLSI architectures which are shown to be quite suitable to handle these operations. These architectures will result in fully pipelined bit-serial arrays which require no control units. Some preliminary implementations indicate a substantial speed-up gain over other existing designs.en_US
dc.format.extent607774 bytes
dc.format.mimetypeapplication/pdf
dc.language.isoen_USen_US
dc.relation.ispartofseriesISR; TR 1985-8en_US
dc.titleVLSI Architectures Based on the Small N Algorithms.en_US
dc.typeTechnical Reporten_US
dc.contributor.departmentISRen_US


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