Silicon-based single electron devices (SEDs), fabricated using gate-defined quantum dots are some of the world’s most sensitive devices. Local charge fluctuations and disorder caused by defects in the oxide or substrate impurities can profoundly affect device operation. While most workers consider the above when fabricating SEDs in the Si MOS system, they do not typically consider strain. The fabrication process of the gate material usually results in a thin film under a significant amount of stress, which locally modulates the silicon conduction band. Additionally, the coefficient of thermal expansion mismatch between typical MOS gate materials, such as aluminum, and the underlying silicon substrate also produces strain, which further modifies the conduction band. For quantum dot devices measured at cryogenic temperatures, this local modification of the conduction band is strong enough to lead to the formation of unintentional quantum dots and to affect the tunnel coupling between dots. To realize the potential of quantum devices, gate-induced strain must be understood so as to be mitigated or exploited.

In this work, we investigate the role of gate-induced strain in quantum dot devices by comparing measurements of the 4-terminal I(V) characteristics of tunnel barrier devices at cryogenic temperatures. From this, we demonstrate a new electrical measurement of gate-induced strain using tunnel junctions (TJs). Our COMSOL simulations of these devices show that the gate-induced strain will modify the barrier height, depending on both the magnitude and sign of inhomogeneous stress. We fabricate MOS devices on bulk silicon wafers with a variety of gate electrodes, including aluminum and titanium. By comparing nearly identical tunnel junction devices fabricated with two different gate materials, Al and Ti, we measure a relative strain difference consistent with our experimentally measured coefficients of thermal expansion. Our results show that the commonly used bulk parameters for simulating strain effects in silicon QDs do not work well in practice.

Additionally, we present measurements of oxide defect densities (fixed charge and interface trap density) as a function of forming gas anneal temperature for three different gate metals: Al, Ti/Pd, and Ti/Pt. We also investigate the effect of these anneals on the mechanical properties of the gate material, such as the intrinsic film stress and coefficient of thermal expansion. The combination of our charge defect and mechanical measurements show that there is no way to simultaneously minimize the effects of both using the forming gas anneal. This result puts tension on designing fabrication processes for MOS QDs where one must choose between setting the anneal such that defects are minimized or the strain-induced modulation of the conduction band is minimized. Additionally, we find that our measured values of the coefficient of thermal expansion deviate significantly from the expected bulk values. This suggests that the common material parameters used to simulate gate-induced strain in MOS QD are not accurate.

Building towards the goal of controlling non-idealities in silicon MOS QDs requires methods of measuring strain under relevant conditions while also finding ways to adjust processing to minimize the impact of other non-idealities. The work in thesis represents a significant step towards that goal. The devices presented easily lend themselves to future work exploring deposition parameters and anneals to manipulate inhomogeneous strain. Our method for measuring relative strain satisfies the sensitivity, spatial resolution and low-temperature requirements relevant for MOS QDs. Moreover, the fabrication and measurements are similar to those for QDs so that this method is directly relevant for QD devices. Our data provide an important step forward in assessing gate-induced strain in QD devices in-situ while highlighting the need for further experimental work and a greater theoretical understanding of the electrostatics and strain behavior.