Electrical & Computer Engineering Research Works

Permanent URI for this collectionhttp://hdl.handle.net/1903/1658

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Start date: 2000End date: 2009

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Now showing 1 - 10 of 72
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    The crosstalk between EGF, IGF, and Insulin cell signaling pathways - computational and experimental analysis
    (Springer Nature, 2009-09-04) Zielinski, Rafal; Przytycki, Pawel F; Zheng, Jie; Zhang, David; Przytycka, Teresa M; Capala, Jacek
    Cellular response to external stimuli requires propagation of corresponding signals through molecular signaling pathways. However, signaling pathways are not isolated information highways, but rather interact in a number of ways forming sophisticated signaling networks. Since defects in signaling pathways are associated with many serious diseases, understanding of the crosstalk between them is fundamental for designing molecularly targeted therapy. Unfortunately, we still lack technology that would allow high throughput detailed measurement of activity of individual signaling molecules and their interactions. This necessitates developing methods to prioritize selection of the molecules such that measuring their activity would be most informative for understanding the crosstalk. Furthermore, absence of the reaction coefficients necessary for detailed modeling of signal propagation raises the question whether simple parameter-free models could provide useful information about such pathways. We study the combined signaling network of three major pro-survival signaling pathways: E pidermal G rowth F actor R eceptor (EGFR), I nsulin-like G rowth F actor-1 R eceptor (IGF-1R), and I nsulin R eceptor (IR). Our study involves static analysis and dynamic modeling of this network, as well as an experimental verification of the model by measuring the response of selected signaling molecules to differential stimulation of EGF, IGF and insulin receptors. We introduced two novel measures of the importance of a node in the context of such crosstalk. Based on these measures several molecules, namely Erk1/2, Akt1, Jnk, p70S6K, were selected for monitoring in the network simulation and for experimental studies. Our simulation method relies on the Boolean network model combined with stochastic propagation of the signal. Most (although not all) trends suggested by the simulations have been confirmed by experiments. The simple model implemented in this paper provides a valuable first step in modeling signaling networks. However, to obtain a fully predictive model, a more detailed knowledge regarding parameters of individual interactions might be necessary.
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    A Comparative Study of Branch Predictors
    (2007) Kotha, Aparna; Barua, Rajeev
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    Power Minimization under QoS Constraints
    (IEEE, 2002-04) Wong, Jennifer L.; Qu, Gang; Potkonjak, Miodrag
    QoS has been often addressed in multimedia, video, and networking research communities, but rarely in the design community. Our goal is to introduce the first system design technique for comprehensive quality-of-service (QoS) low power synthesis. Specifically, we study how to efficiently exploit the trade-o between the system cost and energy consumption in real-time systems that address packet-based multimedia transmission and processing. We first introduce a system of techniques that minimizes energy consumption of stream-oriented applications under two main QoS metrics: latency and synchronization. Speci cally, we study how multiple voltages can be used to simultaneously satisfy hardware requirements and minimize power consumption, while preserving the requested level of QoS, in this case satisfying latency and synchronization requirements. We have developed a provably optimal polynomial time o -line algorithm for multiple volt- age scheduling of single and multiple processes. The o -line algorithm provides lower bounds on achievable power minimization and can be used as a starting point for the development and evaluation of an on-line approach. The effectiveness of the algorithm is demonstrated on a number of multimedia benchmarks.
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    Dual-Processor Design of Energy Efficient Fault-Tolerant System
    (IEEE, 2006-09) Hua, Shaoxiong; Pari, Pushkin R.; Qu, Gang
    A popular approach to guarantee fault tolerance in safety-critical applications is to run the application on two processors. A checkpoint is inserted at the comple- tion of the primary copy. If there is no fault, the sec- ondary processor terminates its execution. Otherwise, should the fault occur, the second processor continues and completes the application before its deadline. In this paper, we study the energy efficiency of such dual- processor system. Specifically, we first derive an opti- mal static voltage scaling policy for single periodic task. We then extend it to multiple periodic tasks based on worst case execution time (WCET) analysis. Finally, we discuss how to further reduce system’s energy con- sumption at run time by taking advantage of the actual execution time which is less than the WCET. Simula- tion on real-life benchmark applications shows that our technique can save up to 80% energy while still provid- ing fault tolerance.
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    VLSI CAD Tool Protection by Birthmarking Design Solutions
    (IEEE, 2005-04) Yuan, Lin; Qu, Gang; Srivastava, Ankur
    Many techniques have been proposed in the past for the protection of VLSI design IPs (intellectual property). CAD tools and algorithms are intensively used in all phases of modern VLSI designs; however, little has been done to protect them. Basically, given a problem P and a solution S, we want to be able to determine whether S is obtained by a particular tool or algorithm. We propose two techniques that intentionally leave some trace or birthmark, which refers to certain easy detectable properties, in the design solutions to facilitate CAD tool tracing and protection. The pre-processing technique provides the ideal protection at the cost of losing control of solution’s quality. The post-processing technique balances the level of protection and design quality. We conduct a case study on how to protect a timing-driven gate duplication algorithm. Experimental results on a large set of MCNC benchmarks confirm that the pre-processing technique results in a significant reduction (about 48%) of the optimization power of the tool, while the post-processing technique has almost no penalty (less than 2%) on the tool’s performance.
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    SENSOR CALIBRATION USING NONPARAMETRIC STATISTICAL CHARACTERIZATION OF ERROR MODELS
    (IEEE, 2004-10) Feng, J.; Qu, G.; Potkonjak, M.
    Calibration is the process of identifying and correcting for the systematic bias component of the error in sensor measurements. Traditionally, calibration has usually been conducted by considering a set of measurements in a single time frame and restricted to linear systems with the assumption of equal-quality sensors and single modality. The basis for the new calibration procedure is to construct a statistical error model that captures the characteristics of the measurement errors. Such an error model can be constructed either off-line or on-line. It is derived using the nonparametric kernel density estimation techniques. We propose four alternatives to make the transition from the constructed error model to the calibration model, which is represented by piecewise polynomials. In addition, statistical validation and evaluation methods such as resubstitution, is used in order to establish the interval of confidence for both the error model and the calibration model. Traces of the distance ranging measurements recorded by in-field deployed sensors are used as our demonstrative example.
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    How Many Solutions Does a SAT Instance Have?
    (IEEE, 2004-05) Pari, Pushkin R.; Yuan, Lin; Qu, Gang
    Our goal is to investigate the solution space of a given Boolean Satisfiability (SAT) instance. In particular, we are interested in determining the size of the solution space – the number of truth assignments that make the SAT instance true – and finding all such truth assignments, if possible. This apparently hard problem has both theoretical and practical values. We propose an exact algorithm based on exhaustive search that Solves the instance Once and Finds All Solutions (SOFAS) and several sampling techniques that estimate the size of the solution space. SOFAS works better for SAT instances of small size with a 5X-100X speed-up over the brute force search algorithm. The sampling techniques estimate the solution space reasonably well for standard SAT benchmarks.
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    ARBITRATE-AND-MOVE PRIMITIVES FOR HIGH THROUGHPUT ON-CHIP INTERCONNECTION NETWORKS
    (IEEE, 2004-05) Balkan, Aydin O.; Vishkin, U.; Qu, Gang
    An n-leaf pipelined balanced binary tree is used for arbitration of order and movement of data from n input ports to one output port. A novel arbitrate-and-move primitive circuit for every node of the tree, which is based on a concept of reduced synchrony that benefits from attractive features of both asynchronous and synchronous designs, is presented. The design objective of the pipelined binary tree is to provide a key building block in a high-throughput mesh-of-trees interconnection network for Explicit Multi Threading (XMT) architecture, a recently introduced parallel computation framework. The proposed reduced synchrony circuit was compared with asynchronous and synchronous designs of arbitrate-and-move primitives. Simulations with 0.18m technology show that compared to an asynchronous design, the proposed reduced synchrony implementation achieves a higher throughput, up to 2 Giga- Requests per second on an 8-leaf binary tree. Our circuit also consumes less power than the synchronous design, and requires less silicon area than both the synchronous and asynchronous designs.
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    VLSI Design IP Protection: Solutions, New Challenges, and Opportunities
    (IEEE, 2006-06) Yuan, Lin; Qu, Gang
    It has been a decade since the need of VLSI design intellectual property (IP) protection was identified [1,2]. The goals of IP protection are 1) to enable IP providers to protect their IPs against unauthorized use, 2) to protect all types of design data used to produce and deliver IPs, 3) to detect the use of IPs, and 4) to trace the use of IPs [3]. There are significant advances from both industry and academic towards these goals. However, do we have solutions to achieve all these goals? What are the current state-of-the-art IP protection techniques? Do they meet the protection requirement designers sought for? What are the (new) challenges and is there any feasible answer to them in the foreseeable future? This paper addresses these questions and provides possible solutions mainly from academia point of view. Several successful industry practice and ongoing efforts are also discussed briefly.