ATTACKING THE TIMINGCAMOUFLAGE+ ALGORITHM

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dc.contributor.advisorSrivastava, Ankuren_US
dc.contributor.authorMittu, Priya Devien_US
dc.contributor.departmentElectrical Engineeringen_US
dc.contributor.publisherDigital Repository at the University of Marylanden_US
dc.contributor.publisherUniversity of Maryland (College Park, Md.)en_US
dc.date.accessioned2022-02-04T06:42:06Z
dc.date.available2022-02-04T06:42:06Z
dc.date.issued2021en_US
dc.description.abstractIn today’s world, sending a design to a third party foundry for fabrication poses aserious threat to one’s intellectual property. To keep designs safe from adversaries, design obfuscation techniques have been developed to protect the IP details of the design. This thesis explains how the previously considered secure algorithm, TimingCamouflage+, can be thwarted and the original circuit can be recovered [1]. By removing wave-pipelining false paths, the TimingCamouflage+ algorithm is reduced to the unsecure TimingCamouflage algorithm [2]. Since the TimingCamouflage algorithm is vulnerable to the TimingSAT attack, this reduction proves that TimingCamouflage+ is also vulnerable to TimingSAT and not a secure camouflaging technique [3]. This thesis describes how wave-pipelining paths can be removed, and this method of handling false paths is tested on various ISCAS89 benchmarks and shown to be both functionally correct and feasible in complexity.en_US
dc.identifierhttps://doi.org/10.13016/aniz-t7eu
dc.identifier.urihttp://hdl.handle.net/1903/28483
dc.language.isoenen_US
dc.subject.pqcontrolledElectrical engineeringen_US
dc.subject.pqcontrolledComputer engineeringen_US
dc.subject.pquncontrolledCamouflagingen_US
dc.subject.pquncontrolledHardware securityen_US
dc.subject.pquncontrolledLockingen_US
dc.subject.pquncontrolledTimingen_US
dc.titleATTACKING THE TIMINGCAMOUFLAGE+ ALGORITHMen_US
dc.typeThesisen_US

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