Optimal Unified Architectures for the Real-Time Computation of Time-Recursive Discrete Sinusoidal Transforms

dc.contributor.authorLiu, K.J. Rayen_US
dc.contributor.authorChiu, Ching-Teen_US
dc.contributor.authorKolagotla, Ravi K.en_US
dc.contributor.authorJaJa, Joseph F.en_US
dc.contributor.departmentISRen_US
dc.date.accessioned2007-05-23T09:53:45Z
dc.date.available2007-05-23T09:53:45Z
dc.date.issued1993en_US
dc.description.abstractAn optimal unified architecture that can efficiently compute the Discrete Cosine, Sine, Hartley, Fourier, Lapped Orthogonal, and Complex Lapped transforms for a continuous input data stream is proposed. This structure uses only half as many multipliers as the previous best known scheme [1]. The proposed architecture is regular, modular, and has only local interconnections in both data and control paths. There is no limitation on the transform size N and only 2N - 2 multipliers are needed for the DCT. The throughput of this scheme is one input sample per clock cycle. We provide a theoretical justification by showing that any discrete transform whose basis functions satisfy the Fundamental recurrence Formula has a second-order autoregressive structure in its filter realization. We also demonstrate that dual generation transform pairs share the same autoregressive structure. We extend these time-recursive concepts to multi- dimensional transforms. The resulting d-dimensional structures are fully- pipelined and consist of only d 1-D transform arrays and shift registers.en_US
dc.format.extent1343757 bytes
dc.format.mimetypeapplication/pdf
dc.identifier.urihttp://hdl.handle.net/1903/5376
dc.language.isoen_USen_US
dc.relation.ispartofseriesISR; TR 1993-31en_US
dc.subjectsignal processingen_US
dc.subjectparallel architecturesen_US
dc.subjectVLSI architecturesen_US
dc.subjectSystems Integrationen_US
dc.titleOptimal Unified Architectures for the Real-Time Computation of Time-Recursive Discrete Sinusoidal Transformsen_US
dc.typeTechnical Reporten_US

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