A NON-INVASIVE ELECTROSTATIC GATING METHOD FOR PROBING TWO-DIMENSIONAL ELECTRON SYSTEMS ON PRISTINE, CHEMICALLY-TERMINATED, INTRINSIC SI SURFACES

Abstract

We have demonstrated a new and effective method for the non-invasive electrostatic gating of pristine, chemically-terminated, intrinsic Si surfaces. This was achieved using a silicon-on-insulator (SOI) device design in which two chips, an SOI gate chip and a pristine, Si chip, are Van der Waals bonded to one another. In this architecture, all harsh device processing is relegated to a single SOI chip which is host to all of the electrical components, including the ohmic contacts and the electrostatic gates. The pristine Si chip is bonded to the ohmic contacts on the SOI chip, while the electrostatic gates on the SOI chip are separated from the Si surface by vacuum. This novel design allows for the Si chip to remain free of dopants or metals that are traditionally fabricated directly onto the surface, thus enabling the Si chip to retain its native properties and remain compatible with a wide variety of existing surface preparation techniques, including wet chemical processing and dry ultra-high vacuum processing. Using our non-invasive architecture, we were able to electrostatically gate a hydrogen-terminated Si(111) (H-Si(111)) surface. Transport measurements were performed on a global-gate induced two-dimensional electron system (2DES) on the H-Si(111) surface via electrical access through the ohmic contacts, while the depletion gates confined the 2DES to a Van der Pauw geometry. We also extended the reach of our devices to probe -- for the first time -- 2D electron transport on a pristine, intrinsic iodine-terminated Si(111) (I-Si(111)) surface. To date, no other 2D magnetotransport measurements have been realized on I-Si(111) surfaces due in large part to the difficulties surrounding the electrostatic gating of these fragile surfaces.

This novel architecture is not without its own set of challenges. In particular, the series contact resistance that arises at the SOI-Si bond edge, especially at low temperatures, is significant. The current injection across a Van der Waals bond is an inherent feature in our architecture due to the placement of the ohmic contacts on the SOI piece. I developed a mathematical framework for understanding this current injection in our devices, and presented device modifications for decreasing the contact resistance.