Design and Implementation of Systolic Architectures for Vector Quantization

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dc.contributor.advisorJaJa, J.en_US
dc.contributor.authorKolagotla, Ravi K.en_US
dc.contributor.departmentISRen_US
dc.date.accessioned2007-05-23T09:52:28Z
dc.date.available2007-05-23T09:52:28Z
dc.date.issued1992en_US
dc.description.abstractVector Quantization has emerged as an efficient data compression tool for compressing speech and image data. We develop efficient systolic architecture implementations of Tree-Search Vector Quantizers (TSVQ) and Finite-State Vector Quantizers (FSVQ). Our TSVQ architecture consists of a linear array of processors, each processor performing the computations required at one level of the binary tree. Encoding is performed in a pipeline fashion with each processor generating a portion of the path through the tree. The final processor returns the complete index. Data and control flow from processor to processor along the pipeline and no global control signals are needed. The FSVQ architecture for image coding consists of a linear array of TSVQ processors with each processor operating on a separate column of the input image. The number of processors needed depends on the latency of the TSVQ and is independent of the size of the image. We also develop implementations of Scalar and Inverse Scalar Quantizers for use in transform coding applications.en_US
dc.format.extent2732770 bytes
dc.format.mimetypeapplication/pdf
dc.identifier.urihttp://hdl.handle.net/1903/5319
dc.language.isoen_USen_US
dc.relation.ispartofseriesISR; PhD 1992-11en_US
dc.subjectdata compressionen_US
dc.subjectimage processingen_US
dc.subjectsignal processingen_US
dc.subjectspeech processingen_US
dc.subjectparallel architecturesen_US
dc.subjectVLSI architecturesen_US
dc.subjectSystems Integrationen_US
dc.titleDesign and Implementation of Systolic Architectures for Vector Quantizationen_US
dc.typeDissertationen_US

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