CAPACITANCE-TO-DIGITAL CONVERTERS FOR HIGH-SPEED HIGH-RESOLUTION READOUT OF CAPACITIVE SENSORS

Abstract

This work focuses on the design of a capacitance-to-digital converter (CDC) for high-speed high-resolution readout of capacitive sensors. Most previously reported CDCs show a tradeoff in resolution and conversion speed; In this work a two-step successive approximation register (SAR) CDC is proposed to improve resolution and conversion speed over state-of-the-art. First, the coarse conversion stage performs a capacitive offset compensation down to within 10fF. The fine conversion stage converts the amplified residue voltage with a resolution of 200aF. These bits are communicated off chip on an I2C bus. The effective number of bits (ENOB) is compared under different measurement conditions. The circuit achieves 9.8 ENOB with a 28 µs conversion time. When overclocked, the circuit achieves 8.2 ENOB with a 14 µs conversion time. This equates to an overall figure of merit (ENOB throughput) of 350 kbits/s and 585 kbits/s, respectively, which is among the highest values reported in the literature. The interface circuit design is described, simulated, and measured to characterize performance.