An Architecture for High-throughput and Improved-quality Stereo Vision Processor

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2010

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Abstract

This paper presents the VLSI architecture to achieve high-throughput and

improved-quality stereo vision for real applications. The stereo vision processor

generates gray-scale output images with depth information from input images taken by

two CMOS Image Sensors (CIS). The depth estimator using the sum of absolute

differences (SAD) algorithm as stereo matching technique is implemented on hardware

by exploiting pipelining and parallelism. To produce depth maps with improved-quality

at real-time, pre- and post-processing units are adopted, and to enhance the adaptability

of the system to real environments, special function registers (SFRs) are assigned to

vision parameters. The design using 0.18um standard CMOS technology can operate at

120MHz clock, achieving over 140 frames/sec depth maps with 320 by 240 image size

and 64 disparity levels. Experimental results based on images taken in real world and

the Middlebury data set will be presented. Comparison data with existing hardware

systems and hardware specifications of the proposed processor will be given.

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