Finite Buffer Realization of Input-Output Discrete Event Systems
| dc.contributor.author | Kumar, Ratnesh | en_US |
| dc.contributor.author | Garg, Vijay K. | en_US |
| dc.contributor.author | Marcus, Steven I. | en_US |
| dc.contributor.department | ISR | en_US |
| dc.date.accessioned | 2007-05-23T09:56:02Z | |
| dc.date.available | 2007-05-23T09:56:02Z | |
| dc.date.issued | 1994 | en_US |
| dc.description.abstract | Many discrete event systems (DESs) such as manufacturing systems, data base management systems, communication networks, traffic systems, etc., can be modeled as input-output discrete event systems (I/O DESs). In this paper we formulate and study the problem of stable realization of such systems in the logical setting. Given an input and an output language describing the sequences of events that occur at the input and the output, respectively, of an I/O DES, we study whether it is possible to realize the system as a unit consisting of a given set of buffers of finite capacity, called a dispatching unit. The notions of stable, conditionally stable, dispatchable and conditionally dispatchable units are introduced as existence of stable (or input-output bounded), and causal (or prefix preserving) input- output maps, and effectively computable necessary and sufficient conditions for testing them are obtained. | en_US |
| dc.format.extent | 138575 bytes | |
| dc.format.mimetype | application/pdf | |
| dc.identifier.uri | http://hdl.handle.net/1903/5484 | |
| dc.language.iso | en_US | en_US |
| dc.relation.ispartofseries | ISR; TR 1994-2 | en_US |
| dc.subject | discrete event dynamical systems | en_US |
| dc.subject | flexible manufacturing | en_US |
| dc.subject | Systems Integration Methodology | en_US |
| dc.title | Finite Buffer Realization of Input-Output Discrete Event Systems | en_US |
| dc.type | Technical Report | en_US |
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