Real-Time Parallel and Fully-Pinelined Two-Dimensional DCT Lattice Structures with Application to HDTV Systems

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dc.contributor.authorChiu, Ching-Teen_US
dc.contributor.authorLiu, K.J. Rayen_US
dc.contributor.departmentISRen_US
dc.date.accessioned2007-05-23T09:48:33Z
dc.date.available2007-05-23T09:48:33Z
dc.date.issued1991en_US
dc.description.abstractThe two-dimensional discrete cosine transform (2-D DCT) has been widely recognized as the most effective technique in image data compression. In this paper, we propose a new algorithm to compute the 2-D DCT from a frame-recursive point of view. Based on this approach, two real-time parallel lattice structures for successive frame and block 2-D DCT are developed. The systems is fully-pipelined with throughput rate N clock cycles for N x N successive input data frame. This is the fastest pipelined structure for the 2-D DCT known so far. Moreover, the 2-D DCT architecture is module, regular, and locally-connected and requires only two 1-D DCT blocks which can be extended directly from the 1-D DCT structure without transposition. Therefore, it is very suitable for VLSI implementation for the high speed HDTV systems. We also propose a parallel 2-D DCT architecture and a new scanning pattern for the HDTV system to achieve higher performance. The VLSI implementation of the 2-D DCT using distributed arithmetics to increase computational efficiency and reduce round off error is also discussed.en_US
dc.format.extent1385495 bytes
dc.format.mimetypeapplication/pdf
dc.identifier.urihttp://hdl.handle.net/1903/5126
dc.language.isoen_USen_US
dc.relation.ispartofseriesISR; TR 1991-78en_US
dc.subjectsignal processingen_US
dc.subjectalgorithmsen_US
dc.subjectparallel architecturesen_US
dc.subjectVLSI architecturesen_US
dc.subjectSystems Integrationen_US
dc.titleReal-Time Parallel and Fully-Pinelined Two-Dimensional DCT Lattice Structures with Application to HDTV Systemsen_US
dc.typeTechnical Reporten_US

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