Integrating a Dual-Vth Design Flow Using Mixed Vth Cell Libraries in EDA Tool
| dc.contributor.advisor | Qu, Gang | en_US |
| dc.contributor.author | Nagarajan, Chandra S | en_US |
| dc.contributor.department | Electrical Engineering | en_US |
| dc.contributor.publisher | Digital Repository at the University of Maryland | en_US |
| dc.contributor.publisher | University of Maryland (College Park, Md.) | en_US |
| dc.date.accessioned | 2007-09-28T14:57:08Z | |
| dc.date.available | 2007-09-28T14:57:08Z | |
| dc.date.issued | 2007-06-04 | en_US |
| dc.description.abstract | Leakage power has become one of the most important components of power dissipation in sub-micron designs. It is critical to include leakage mitigation methods in the low power design flow. Dual-Vth assignment, an effective leakage reduction technique, has been adopted by industrial EDA tools in gate-level design. This thesis presents a dual-Vth based low leakage design flow using a mixed Vth standard cell library, in which transistors within a cell have different Vth values. A mixed threshold standard cell design methodology is implemented and the cells are characterized using HSPICE with 130nm model. We integrated the design flow in a state-of-the-art industrial CAD tool and ran experiments on eleven ISCAS benchmarks and three industrial designs. On an average, our method can achieve 40% leakage saving over designs with nominal threshold voltage cells and 9% saving over the cell-based dual-Vth assignment technique, without any delay penalty. | en_US |
| dc.format.extent | 369980 bytes | |
| dc.format.mimetype | application/pdf | |
| dc.identifier.uri | http://hdl.handle.net/1903/7185 | |
| dc.language.iso | en_US | |
| dc.subject.pqcontrolled | Engineering, Electronics and Electrical | en_US |
| dc.title | Integrating a Dual-Vth Design Flow Using Mixed Vth Cell Libraries in EDA Tool | en_US |
| dc.type | Thesis | en_US |
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