A New Physics-of-Failure Based VLSI Circuits Reliability Simulation and Prediction Methodology

Abstract

It has long been a challenge for reliability engineers to provide accurate VLSI circuits reliability simulation and prediction. The decreasing feature sizes, coupled with non-ideal voltage scaling, raises new reliability concerns such as negative bias temperature instability (NBTI) and adversely affects those long-existed failure mechanisms: electromigration (EM), hot carrier degradation (HCD) and time dependent dielectric breakdown (TDDB). The multiple failure mechanisms effect, together with the increasing circuit complexity make the prediction more difficult to tackle with.

A new physics-of-failure based VLSI circuit reliability prediction methodology is proposed to handle the simulation and prediction challenges. The new methodology takes an unique top-down, bottom-up approach to reduce the modeling and simulation complexity. Detailed application breakdown reveals the cell's operation profile. Cell-level reliability characterization provides accurate operation-based dynamic stress modeling by utilizing the physics-of-failure models. For each failure mechanism, the best-fit lifetime distribution is selected to provide reliability prediction. The application-specific circuit reliability is further predicted by considering the system structure.

A 90nm 64Kb SRAM module is designed and used as an example to demonstrate the prediction methodology. With the given application profile, simulation results showed that TDDB is the most serious reliability concern for the SRAM bit cell, NBTI is in the second place, and HCD has a negligible degradation effect. The memory core's reliability prediction shows the core has a low constant failure rate (2.90E-4 FIT) before 5.8E+4 hours, and an increasing failure rate after that because NBTI wearout starts to kick in.