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dc.contributor.advisorRubloff, Gary W.en_US
dc.contributor.authorPark, SunJunen_US
dc.date.accessioned2007-05-23T10:07:49Z
dc.date.available2007-05-23T10:07:49Z
dc.date.issued1999en_US
dc.identifier.urihttp://hdl.handle.net/1903/6053
dc.description.abstractThis report explains the development of the new Wafer Yield simulation.It shows the user the various effects of numerous factors in manufacturingon total yield, the algorithms behind it, an explanation of the OLE systemthat allows the transfers to occur, the reasoning behind the selectedmeans of presenting the data, and future directions of the project.en_US
dc.format.extent205896 bytes
dc.format.mimetypeapplication/pdf
dc.language.isoen_USen_US
dc.relation.ispartofseriesISR; UG 1999-3en_US
dc.subjectknowledge representationen_US
dc.subjectmanufacturingen_US
dc.subjectmicroprocessorsen_US
dc.subjecttraining simulationsen_US
dc.subjecthuman-computer interface,en_US
dc.titleREU Report: Process Integration with Wafer Yield: An Exercise in Computer-Based Modulesen_US
dc.typeThesisen_US
dc.contributor.departmentISRen_US


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