REU Report: Process Integration with Wafer Yield: An Exercise in Computer-Based Modules
| dc.contributor.advisor | Rubloff, Gary W. | en_US |
| dc.contributor.author | Park, SunJun | en_US |
| dc.contributor.department | ISR | en_US |
| dc.date.accessioned | 2007-05-23T10:07:49Z | |
| dc.date.available | 2007-05-23T10:07:49Z | |
| dc.date.issued | 1999 | en_US |
| dc.description.abstract | This report explains the development of the new Wafer Yield simulation.It shows the user the various effects of numerous factors in manufacturingon total yield, the algorithms behind it, an explanation of the OLE systemthat allows the transfers to occur, the reasoning behind the selectedmeans of presenting the data, and future directions of the project. | en_US |
| dc.format.extent | 205896 bytes | |
| dc.format.mimetype | application/pdf | |
| dc.identifier.uri | http://hdl.handle.net/1903/6053 | |
| dc.language.iso | en_US | en_US |
| dc.relation.ispartofseries | ISR; UG 1999-3 | en_US |
| dc.subject | knowledge representation | en_US |
| dc.subject | manufacturing | en_US |
| dc.subject | microprocessors | en_US |
| dc.subject | training simulations | en_US |
| dc.subject | human-computer interface, | en_US |
| dc.title | REU Report: Process Integration with Wafer Yield: An Exercise in Computer-Based Modules | en_US |
| dc.type | Thesis | en_US |
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