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Systolic Architectures for Signal Compression and Discrimination

dc.contributor.advisorJaJa, J.F.en_US
dc.contributor.authorYu, S-S.en_US
dc.date.accessioned2007-05-23T09:57:38Z
dc.date.available2007-05-23T09:57:38Z
dc.date.issued1994en_US
dc.identifier.urihttp://hdl.handle.net/1903/5565
dc.description.abstractIn this dissertation we propose systolic architectures for several classes of signal processing computations including schemes based on vector quantization and high order crossings techniques. The systolic concept is adapted to design architectures that are simple, regular, and that achieve high concurrency, local communication, and high throughput. Our tree- structured vector quantization (TSVQ) architecture is composed of a linear array of processors, each processor performing the computations required at one level of the binary tree. Encoding is performed in a pipelined fashion with each processor contributing a portion of the path decision through the tree until the final processor is reached to get the complete index. The predictive TSVQ (PTSVQ) architecture for real-time video coding applications uses pipelined arithmetic components to speed up the computation and to provide for regularity in design. This high throughput architecture is suitable for implementing a fully pipelined real-time PTSVQ system. Data and control flow in both architectures flow in a pipelined fashion and no global control signals are needed. We also present a class of architectures for performing signal discrimination and classification based on higher order crossing (HOC) methods. We also present a detailed design of a prototype HOC PCB system using off-the shelf components that can be used for non-destructive testing.en_US
dc.format.extent2948230 bytes
dc.format.mimetypeapplication/pdf
dc.language.isoen_USen_US
dc.relation.ispartofseriesISR; PhD 1994-7en_US
dc.subjectdata compressionen_US
dc.subjectsignal processingen_US
dc.subjectVLSI architecturesen_US
dc.subjectSystems Integrationen_US
dc.titleSystolic Architectures for Signal Compression and Discriminationen_US
dc.typeDissertationen_US
dc.contributor.departmentISRen_US


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