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Area-Efficient Switched Capacitor Filters: Very Large Time- Constant Circuits

dc.contributor.authorLin, Jyhfongen_US
dc.contributor.authorEdwards, Thomasen_US
dc.contributor.authorShamma, Shihaben_US
dc.description.abstractThe detailed theoretical analysis of very large time-constant (VLT) integrators which use either charge elimination (T-cell and Huang's integrators) or charge cancellation (Nagaraj's and charge-differencing integrators) and described. Using a new area- efficient design, the charge-differencing (CD) integrator, the capacitance spread ratio can be easily reduced to less than the reciprocal of the square root of the product of the pole frequency and the sampling period. Non-ideal effects of op-amp like finite DC gain and offset voltage can also be compensated by employing offset storing capacitor operating only with the bi- phase clocking scheme.en_US
dc.format.extent645928 bytes
dc.relation.ispartofseriesISR; TR 1992-64en_US
dc.subjectswitched capacitor circuitsen_US
dc.subjectCommunication en_US
dc.subjectSignal Processing Systemsen_US
dc.titleArea-Efficient Switched Capacitor Filters: Very Large Time- Constant Circuitsen_US
dc.typeTechnical Reporten_US

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