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VLSI Implementation of Real-Time Parallel DCT/DST Lattice Structures for Video

dc.contributor.authorChiu, Ching-Teen_US
dc.contributor.authorKolagotla, Ravi K.en_US
dc.contributor.authorLiu, K.J. Rayen_US
dc.contributor.authorJaJa, Joseph F.en_US
dc.date.accessioned2007-05-23T09:50:25Z
dc.date.available2007-05-23T09:50:25Z
dc.date.issued1992en_US
dc.identifier.urihttp://hdl.handle.net/1903/5216
dc.description.abstractThe alternate use [1] of the discrete cosine transform (DCT) and the discrete sine transform (DST) can achieve a higher data compression rate and less block effect in image processing. A parallel lattice structure that can dually generate the 1-D DCT and DST is proposed. We also develop a fully-pipelined 2-D DCT lattice architecture that consists of two 1-D DCT/DST arrays without transposition. Both architectures are ideally suited for VLSI implementation because they are modular, regular, and have only local interconnections. the VLSI implementation of the lattice module using the distributed arithmetic approach is described. This realization of the lattice module using 2 um CMOS technology can achieve an 80Mb/s data rate.en_US
dc.format.extent1813988 bytes
dc.format.mimetypeapplication/pdf
dc.language.isoen_USen_US
dc.relation.ispartofseriesISR; TR 1992-34en_US
dc.subjectsignal processingen_US
dc.subjectparallel architecturesen_US
dc.subjectVLSI architecturesen_US
dc.subjectSystems Integrationen_US
dc.titleVLSI Implementation of Real-Time Parallel DCT/DST Lattice Structures for Videoen_US
dc.typeTechnical Reporten_US
dc.contributor.departmentISRen_US


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