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    Systolic Architectures for Finite-State Vector Quantization

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    TR_91-102.pdf (739.7Kb)
    No. of downloads: 1013

    Date
    1991
    Author
    Kolagotla, Ravi K.
    Yu, S-S.
    JaJa, Joseph F.
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    Abstract
    We present a new systolic architecture for implementing Finite State Vector Quantization in real-time for both speech and image data. This architecture is modular and has a very simple control flow. Only one processor is needed for speech compression. A linear array of processors is used for image compression; the number of processors needed is independent of the size of the image. We also present a simple architecture for converting line- scanned image data into the format required by this systolic architecture. Image data is processed at a rate of 1 pixel per clock cycle. An implementation at 31.5 MHz can quantize 1024 x 1024 pixel images at 30 frames/sec in real-time. We describe a VLSI implementation of these FSTSVQ processors.
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    http://hdl.handle.net/1903/5148
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