Systolic Architectures for Finite-State Vector Quantization
| dc.contributor.author | Kolagotla, Ravi K. | en_US |
| dc.contributor.author | Yu, S-S. | en_US |
| dc.contributor.author | JaJa, Joseph F. | en_US |
| dc.contributor.department | ISR | en_US |
| dc.date.accessioned | 2007-05-23T09:48:58Z | |
| dc.date.available | 2007-05-23T09:48:58Z | |
| dc.date.issued | 1991 | en_US |
| dc.description.abstract | We present a new systolic architecture for implementing Finite State Vector Quantization in real-time for both speech and image data. This architecture is modular and has a very simple control flow. Only one processor is needed for speech compression. A linear array of processors is used for image compression; the number of processors needed is independent of the size of the image. We also present a simple architecture for converting line- scanned image data into the format required by this systolic architecture. Image data is processed at a rate of 1 pixel per clock cycle. An implementation at 31.5 MHz can quantize 1024 x 1024 pixel images at 30 frames/sec in real-time. We describe a VLSI implementation of these FSTSVQ processors. | en_US |
| dc.format.extent | 757502 bytes | |
| dc.format.mimetype | application/pdf | |
| dc.identifier.uri | http://hdl.handle.net/1903/5148 | |
| dc.language.iso | en_US | en_US |
| dc.relation.ispartofseries | ISR; TR 1991-102 | en_US |
| dc.subject | data compression | en_US |
| dc.subject | image processing | en_US |
| dc.subject | signal processing | en_US |
| dc.subject | speech processing | en_US |
| dc.subject | vector quantization | en_US |
| dc.subject | algorithms | en_US |
| dc.subject | parallel architectures | en_US |
| dc.subject | VLSI architectures | en_US |
| dc.subject | systolic architectures | en_US |
| dc.subject | Systems Integration | en_US |
| dc.title | Systolic Architectures for Finite-State Vector Quantization | en_US |
| dc.type | Technical Report | en_US |
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