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VLSI Implementation of a Tree Searched Vector Quantizer

dc.contributor.authorKolagotla, Ravi K.en_US
dc.contributor.authorYu, S.S.en_US
dc.contributor.authorJaJa, Joseph F.en_US
dc.description.abstractThe VLSI design and implementation of a Tree Searched Vector Quantizer is presented. The number of processors needed is equal to the depth of the tree. All processors are identical and data flow between processors is regular. No global control signals are needed. The processors have been fabricated using MOSIS' 2mm N- well process on a 7.9mm x 9.2mm die. Each processor chip contains 25,000 transistors and has 84 pins. The processors have been thoroughly tested at a clock frequency of 10 MHz. These processors will be used in an adaptive image compression system to compress LANDSAT images.en_US
dc.format.extent546163 bytes
dc.relation.ispartofseriesISR; TR 1990-74en_US
dc.subjectdata compressionen_US
dc.subjectimage processingen_US
dc.subjectVLSI architecturesen_US
dc.subjectSystems Integrationen_US
dc.titleVLSI Implementation of a Tree Searched Vector Quantizeren_US
dc.typeTechnical Reporten_US

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