VLSI Implementation of a Tree Searched Vector Quantizer

dc.contributor.author	Kolagotla, Ravi K.	en_US
dc.contributor.author	Yu, S.S.	en_US
dc.contributor.author	JaJa, Joseph F.	en_US
dc.contributor.department	ISR	en_US
dc.date.accessioned	2007-05-23T09:46:31Z
dc.date.available	2007-05-23T09:46:31Z
dc.date.issued	1990	en_US
dc.description.abstract	The VLSI design and implementation of a Tree Searched Vector Quantizer is presented. The number of processors needed is equal to the depth of the tree. All processors are identical and data flow between processors is regular. No global control signals are needed. The processors have been fabricated using MOSIS' 2mm N- well process on a 7.9mm x 9.2mm die. Each processor chip contains 25,000 transistors and has 84 pins. The processors have been thoroughly tested at a clock frequency of 10 MHz. These processors will be used in an adaptive image compression system to compress LANDSAT images.	en_US
dc.format.extent	546163 bytes
dc.format.mimetype	application/pdf
dc.identifier.uri	http://hdl.handle.net/1903/5022
dc.language.iso	en_US	en_US
dc.relation.ispartofseries	ISR; TR 1990-74	en_US
dc.subject	data compression	en_US
dc.subject	image processing	en_US
dc.subject	VLSI architectures	en_US
dc.subject	Systems Integration	en_US
dc.title	VLSI Implementation of a Tree Searched Vector Quantizer	en_US
dc.type	Technical Report	en_US

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