Bats have long fascinated both scientists and engineers due to their superb ability to use echolocation to fly with speed and agility through complex natural environments in complete darkness. This dissertation presents a neuromorphic VLSI circuit model of bat azimuthal echolocation. Interaural level differences (ILDs) are the cues for bat azimuthal echolocation and are also the primary cues used by other mammals to localize high frequency sounds. The fact that neurons in bats respond to short echoes by one or two spikes strongly suggests that the conventionally used firing rate is an unlikely code. The operation of first spike latency in ILD computation and transformation is investigated in a network of spiking neurons linking the lateral superior olive (LSO), dorsal nucleus of the lateral lemniscus (DNLL), and inferior colliculus (IC). The results of the investigation suggest that spatially distributed first spike latencies can serve as a fast code for azimuth that can be ``read-out'' by ascending stages. With the hardware echolocation model that uses spike timing representation, we study how multiple echoes can affect bat echolocation and demonstrate that the response to multiple sounds is not a simple linear addition of the response to single sounds. By developing functional models of the bat echolocation system, we can study the efficient implementation demonstrated by nature. For example, variations among analog VLSI circuit units due to the unavoidable transistor mismatch - traditionally thought of as a hurdle to overcome - have been found beneficial in generating the desired diversity of response that is similar to their neural counterparts. This work advocates the use and design of summating and exponentially decaying synapses. A compact and easily controllable synapse circuit has found an application in achieving a linear temporal spike summation by operating with a very short time constants. It has also been applied in modeling a nonlinear intensity-latency trading by working with a long synaptic time constant. We propose a new synapse circuit model that is compatible with those used in computational models and implementable by CMOS transistors operating in the subthreshold region.