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    FBsim and the Fully Buffered DIMM Memory System Architecture

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    No. of downloads: 984

    Date
    2005-05-03
    Author
    Nasr, Rami Marwan
    Advisor
    Jacob, Bruce L
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    Abstract
    As DRAM device data rates increase in chase of ever increasing memory request rates, parallel bus limitations and cost constraints require a sharp decrease in load on the multi-drop buses between the devices and the memory controller, thus limiting the memory system's scalability and failing to meet the capacity requirements of modern server and workstation applications. A new technology, the Fully Buffered DIMM architecture is currently being introduced to address these challenges. FB-DIMM uses narrower, faster, buffered point to point channels to meet memory capacity and throughput requirements at the price of latency. This study provides a detailed look at the proposed architecture and its adoption, introduces an FB-DIMM simulation model - the FBSim simulator - and uses it to explore the design space of this new technology - identifying and experimentally proving some of its strengths, weaknesses and limitations, and uncovering future paths of academic research into the field.
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    http://hdl.handle.net/1903/2565
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    • Electrical & Computer Engineering Theses and Dissertations
    • UMD Theses and Dissertations

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