FBsim and the Fully Buffered DIMM Memory System Architecture

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dc.contributor.advisorJacob, Bruce Len_US
dc.contributor.authorNasr, Rami Marwanen_US
dc.contributor.departmentElectrical Engineeringen_US
dc.contributor.publisherDigital Repository at the University of Marylanden_US
dc.contributor.publisherUniversity of Maryland (College Park, Md.)en_US
dc.date.accessioned2005-08-03T14:53:22Z
dc.date.available2005-08-03T14:53:22Z
dc.date.issued2005-05-03en_US
dc.description.abstractAs DRAM device data rates increase in chase of ever increasing memory request rates, parallel bus limitations and cost constraints require a sharp decrease in load on the multi-drop buses between the devices and the memory controller, thus limiting the memory system's scalability and failing to meet the capacity requirements of modern server and workstation applications. A new technology, the Fully Buffered DIMM architecture is currently being introduced to address these challenges. FB-DIMM uses narrower, faster, buffered point to point channels to meet memory capacity and throughput requirements at the price of latency. This study provides a detailed look at the proposed architecture and its adoption, introduces an FB-DIMM simulation model - the FBSim simulator - and uses it to explore the design space of this new technology - identifying and experimentally proving some of its strengths, weaknesses and limitations, and uncovering future paths of academic research into the field.en_US
dc.format.extent3097607 bytes
dc.format.mimetypeapplication/pdf
dc.identifier.urihttp://hdl.handle.net/1903/2565
dc.language.isoen_US
dc.subject.pqcontrolledEngineering, Electronics and Electricalen_US
dc.subject.pqcontrolledComputer Scienceen_US
dc.subject.pquncontrolledFB-DIMMen_US
dc.subject.pquncontrolledFully Buffereden_US
dc.subject.pquncontrolledDRAMen_US
dc.subject.pquncontrolledDRAM Architectureen_US
dc.subject.pquncontrolledSerial Interconnecten_US
dc.titleFBsim and the Fully Buffered DIMM Memory System Architectureen_US
dc.typeThesisen_US

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