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shi, zhen
Sandborn, Peter
ABSTRACT Title of Dissertation: OPTIMIZATION OF TEST/DIAGNOSIS/REWORK LOCATION(S) AND CHARACTERISTICS IN ELECTRONIC SYSTEMS ASSEMBLY Zhen Shi, Doctor of Philosophy, 2004 Dissertation directed by: Associate Professor Peter A. Sandborn Department of Mechanical Engineering For electronic systems it is not uncommon for 60% or more of the recurring cost to be associated with testing. Performing tradeoffs associated with where in a process to test and what level of test, diagnosis and rework to perform are key to optimizing the cost and yield of an electronic system's assembly. In this dissertation, a methodology that uses a real-coded genetic algorithm has been developed to minimize the yielded cost of electronic products by optimizing the locations of test, diagnosis and rework operations and their characteristics. This dissertation presents a test, diagnosis, and rework analysis model for use in electronic systems assembly. The approach includes a model of functional test operations characterized by fault coverage, false positives, and defects introduced in test; in addition, rework and diagnosis operations (diagnostic test) have variable success rates and their own defect introduction mechanisms. The model accommodates multiple rework attempts on a product instance. For use in practical assembly processes, the model has been extended by defining a general form of the relationship between test cost and fault coverage. The model is applied within a framework for optimizing the location(s) and characteristics (fault coverage/test cost and rework attempts) of Test/Diagnosis/Rework (TDR) operations in a general assembly process. A new search algorithm called Waiting Sequence Search (WSS) is applied to traverse a general process flow to perform the cumulative calculation of a yielded cost objective function. Real-Coded Genetic Algorithms (RCGAs) are used to perform a multi-variable optimization that minimizes yielded cost. Several simple cases are analyzed for validation and general complex process flows are used to demonstrate the applicability of the algorithm. A real multichip module (MCM) manufacturing and assembly process is used to demonstrate that the optimization methodology developed in this dissertation can find test and rework solutions that have lower yielded cost than solutions calculated by manually choosing the test strategies and characteristics. The optimization methodology with Monte Carlo methods included for the process flow under uncertain inputs is also addressed in this dissertation. It is anticipated that this research will improve the ability of manufacturing engineers to place TDR operations in a process flow. The ability to optimize the TDR operations can also be used as a feedback to a Design for Test (DFT) analysis of the electronic systems showing which portion of the system should be redesigned to accommodate testing for a higher level of fault coverage, and where there is less need for test.