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dc.contributor.advisorSrivastava, Ankur
dc.contributor.advisorYeung, Donald
dc.contributor.authorSerafy, Caleb
dc.contributor.authorSrivastava, Ankur
dc.contributor.authorYeung, Donald
dc.date.accessioned2015-12-14T15:56:05Z
dc.date.available2015-12-14T15:56:05Z
dc.date.issued2015-12
dc.identifierhttps://doi.org/10.13016/M2QX40
dc.identifier.urihttp://hdl.handle.net/1903/17180
dc.description.abstractDesign space exploration (DSE) is becoming increasingly complex as the number of tunable design parameters increases in cutting edge CPU designs. The advent of 3D integration compounds the problem by expanding the architectural design space, causing intricate links between memory and logic behavior and increasing the interdependence between physical and architectural design. Exhaustive simulation of an architectural design space has become computationally infeasible, and previous work has proposed fast DSE methodologies using modeling or pseudo-simulation. Modeling techniques can be used to predict design space properties by regression fitting. However in the past such techniques have only been applied to optimization metrics such as performance or energy efficiency while physical constraints have been ignored. We propose a technique to apply spline modeling on a 3D CPU design space to predict optimization metrics and physical design properties (e.g. power, area and temperature). We use these models to identify optimal 3D CPU architectures subject to physical constraints while drastically reducing simulation time compared to exhaustive simulation. We show that our technique is able to identify design points within 0.5% of the global optimal while simulating less than 5% of the design space.en_US
dc.description.sponsorshipNSF Grant CCF1302375 DARPA IceCoolen_US
dc.language.isoen_USen_US
dc.relation.ispartofseriesISR;TR_2015-06
dc.subject3D CPUen_US
dc.subjectDesign Space Explorationen_US
dc.subjectRegression Modelingen_US
dc.subjectPhysically Constrained Designen_US
dc.subjectStacked DRAMen_US
dc.titlePhysically Constrained Design Space Modeling for 3D CPUsen_US
dc.typeTechnical Reporten_US
dc.relation.isAvailableAtInstitute for Systems Researchen_us
dc.relation.isAvailableAtDigital Repository at the University of Marylanden_us
dc.relation.isAvailableAtUniversity of Maryland (College Park, MD)en_us


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