Physically Constrained Design Space Modeling for 3D CPUs
| dc.contributor.advisor | Srivastava, Ankur | |
| dc.contributor.advisor | Yeung, Donald | |
| dc.contributor.author | Serafy, Caleb | |
| dc.contributor.author | Srivastava, Ankur | |
| dc.contributor.author | Yeung, Donald | |
| dc.date.accessioned | 2015-12-14T15:56:05Z | |
| dc.date.available | 2015-12-14T15:56:05Z | |
| dc.date.issued | 2015-12 | |
| dc.description.abstract | Design space exploration (DSE) is becoming increasingly complex as the number of tunable design parameters increases in cutting edge CPU designs. The advent of 3D integration compounds the problem by expanding the architectural design space, causing intricate links between memory and logic behavior and increasing the interdependence between physical and architectural design. Exhaustive simulation of an architectural design space has become computationally infeasible, and previous work has proposed fast DSE methodologies using modeling or pseudo-simulation. Modeling techniques can be used to predict design space properties by regression fitting. However in the past such techniques have only been applied to optimization metrics such as performance or energy efficiency while physical constraints have been ignored. We propose a technique to apply spline modeling on a 3D CPU design space to predict optimization metrics and physical design properties (e.g. power, area and temperature). We use these models to identify optimal 3D CPU architectures subject to physical constraints while drastically reducing simulation time compared to exhaustive simulation. We show that our technique is able to identify design points within 0.5% of the global optimal while simulating less than 5% of the design space. | en_US |
| dc.description.sponsorship | NSF Grant CCF1302375 DARPA IceCool | en_US |
| dc.identifier | https://doi.org/10.13016/M2QX40 | |
| dc.identifier.uri | http://hdl.handle.net/1903/17180 | |
| dc.language.iso | en_US | en_US |
| dc.relation.isAvailableAt | Institute for Systems Research | en_us |
| dc.relation.isAvailableAt | Digital Repository at the University of Maryland | en_us |
| dc.relation.isAvailableAt | University of Maryland (College Park, MD) | en_us |
| dc.relation.ispartofseries | ISR;TR_2015-06 | |
| dc.subject | 3D CPU | en_US |
| dc.subject | Design Space Exploration | en_US |
| dc.subject | Regression Modeling | en_US |
| dc.subject | Physically Constrained Design | en_US |
| dc.subject | Stacked DRAM | en_US |
| dc.title | Physically Constrained Design Space Modeling for 3D CPUs | en_US |
| dc.type | Technical Report | en_US |