Mechanical Engineering
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Item Investigation into the Influence of Build Parameters on Failure of 3D Printed Parts(2016) Fornasini, Giacomo; Schmidt, Linda C; Mechanical Engineering; Digital Repository at the University of Maryland; University of Maryland (College Park, Md.)Additive manufacturing, including fused deposition modeling (FDM), is transforming the built world and engineering education. Deep understanding of parts created through FDM technology has lagged behind its adoption in home, work, and academic environments. Properties of parts created from bulk materials through traditional manufacturing are understood well enough to accurately predict their behavior through analytical models. Unfortunately, Additive Manufacturing (AM) process parameters create anisotropy on a scale that fundamentally affects the part properties. Understanding AM process parameters (implemented by program algorithms called slicers) is necessary to predict part behavior. Investigating algorithms controlling print parameters (slicers) revealed stark differences between the generation of part layers. In this work, tensile testing experiments, including a full factorial design, determined that three key factors, width, thickness, infill density, and their interactions, significantly affect the tensile properties of 3D printed test samples.Item Detection of Interconnect Failure Precursors using RF Impedance Analysis(2010) Kwon, Daeil; Pecht, Michael G; Mechanical Engineering; Digital Repository at the University of Maryland; University of Maryland (College Park, Md.)Many failures in electronics result from the loss of electrical continuity of common board-level interconnects such as solder joints. Measurement methods based on DC resistance such as event detectors and data-loggers have long been used by the electronics industry to monitor the reliability of interconnects during reliability testing. DC resistance is well-suited for characterizing electrical continuity, such as identifying an open circuit, but it is not useful for detecting a partially degraded interconnect. Degradation of interconnects, such as cracking of solder joints due to fatigue or shock loading, usually initiates at an exterior surface and propagates towards the interior. A partially degraded interconnect can cause the RF impedance to increase due to the skin effect, a phenomenon wherein signal propagation at frequencies above several hundred MHz is concentrated at the surface of a conductor. Therefore, RF impedance exhibits greater sensitivity compared to DC resistance in detecting early stages of interconnect degradation and provides a means to prevent and predict an important cause of electronics failures. This research identifies the applicability of RF impedance as a means of a failure precursor that allows for prognostics on interconnect degradation based on electrical measurement. It also compares the ability of RF impedance with that of DC resistance to detect early stages of interconnect degradation, and to predict the remaining life of an interconnect. To this end, RF impedance and DC resistance of a test circuit were simultaneously monitored during interconnect stress testing. The test vehicle included an impedance-controlled circuit board on which a surface mount component was soldered using two solder joints at the end terminations. During stress testing, the RF impedance exhibited a gradual non-linear increase in response to the early stages of solder joint cracking while the DC resistance remained constant. The gradual increase in RF impedance was trended using prognostic algorithms in order to predict the time to failure of solder joints. This prognostic approach successfully predicted solder joint remaining life with a prediction error of less than 3%. Furthermore, it was demonstrated both theoretically and experimentally that the RF impedance analysis was able to distinguish between two competing interconnect failure mechanisms: solder joint cracking and pad cratering. These results indicate that RF impedance provides reliable interconnect failure precursors that can be used to predict interconnect failures. Since the performance of high speed devices is adversely affected by early stages of interconnect degradation, RF impedance analysis has the potential to provide improved reliability assessment for these devices, as well as accurate failure prediction for current and future electronics.Item Failure Mechanisms in Wideband Semiconductor Power Devices(2006-06-05) Zhang, Xiaohu; Bernstein, Joseph; Mechanical Engineering; Digital Repository at the University of Maryland; University of Maryland (College Park, Md.)Silicon carbide (SiC), as one of the wide bandgap semiconductors, is a promising material for next-generation power devices due to its high critical electric field, high thermal conductivity, and high saturated electron drift velocity properties. Extensive studies have been focused their electrical characterizations. Failure mechanisms of SiC devices, however, have not been fully explored. In this work the failure mechanisms of SiC power devices, including Schottky diodes, power MOSFETs and IGBTs, are investigated. The characteristics of SiC Schottky diodes have been investigated and simulated based on the drift-diffusion model. Interface state degradation has been identified as the mechanism responsible for the non-catastrophic failure happened in Schottky diode. Experimental and simulation results are provided to support this conclusion. Single-event burnout (SEB) and single-event gate rupture (SEGR) failure mechanisms have been investigated for SiC power MOSFETS in details in this work since power MOSFETs have been used in very critical applications. The features of SiC power MOSFET SEB and SEGR failures have been simulated successfully and compared to those of Si power MOSFETs. The much better robustness of SiC power MOSFES against SEB failures has been demonstrated by the simulation results. At last the latch-up failure mechanism has been investigated for SiC IGBTs. Compared to Si IGBTs, the results show that SiC IGBTs have a stronger capability against the latch-up failure. The design and application guideline for SiC power devices can be made base on the results obtained in this work.Item DEEP SUBMICRON CMOS VLSI CIRCUIT RELIABILITY MODELING, SIMULATION AND DESIGN(2005-11-29) Li, Xiaojun; Bernstein, Joseph B; Mechanical Engineering; Digital Repository at the University of Maryland; University of Maryland (College Park, Md.)CMOS VLSI circuit reliability modeling and simulation have attracted intense research interest in the last two decades, and as a result almost all IC Design For Reliability (DFR) tools now try to incrementally simulate device wearout mechanisms in iterative ways. These DFR tools are capable of accurately characterizing the device wearout process and predicting its impact on circuit performance. Nevertheless, excessive simulation time and tedious parameter testing process often limit popularity of these tools in product design and fabrication. This work develops a new SPICE reliability simulation method that shifts the focus of reliability analysis from device wearout to circuit functionality. A set of accelerated lifetime models and failure equivalent circuit models are proposed for the most common MOSFET intrinsic wearout mechanisms, including Hot Carrier Injection (HCI), Time Dependent Dielectric Breakdown (TDDB), and Negative Bias Temperature Instability (NBTI). The accelerated lifetime models help to identify the most degraded transistors in a circuit in terms of the device's terminal voltage and current waveforms. Then corresponding failure equivalent circuit models are incorporated into the circuit to substitute these identified transistors. Finally, SPICE simulation is performed again to check circuit functionality and analyze the impact of device wearout on circuit operation. Device wearout effects are lumped into a very limited number of failure equivalent circuit model parameters, and circuit performance degradation and functionality are determined by the magnitude of these parameters. In this new method, it is unnecessary to perform a large number of small-step SPICE simulation iterations. Therefore, simulation time is obviously shortened in comparison to other tools. In addition, a reduced set of failure equivalent circuit model parameters, rather than a large number of device SPICE model parameters, need to be accurately characterized at each interim wearout process. Thus device testing and parameter extraction work are also significantly simplified. These advantages will allow circuit designers to perform quick and efficient circuit reliability analyses and to develop practical guidelines for reliable electronic designs.